K. Imai

发表

A novel filtering method to extract three critical yield loss components (gross, repeated, and random) FIMER

K. Imai, T. Kaga, 2000 .

An interpolative PCM CODEC with multiplexed digital filters

Hiroshi Kuwahara, Hirotoshi Shirasu, T. Okabe, 1980 .

60-nm Gate Length SOI CMOS Technology Optimized for "System-on-a-SOI-Chip" Solution

Jong-Wook Lee, Shin Yokoyama, Shinya Maruyama, 2003 .

A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

A. Ono, K. Imai, K. Noda, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Design Methodology of Body-Biasing Scheme for Low Power System LSI With Multi- $V_{\rm th}$ Transistors

K. Imai, Y. Yamagata, Y. Goto, 2007, IEEE Transactions on Electron Devices.

Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

T. Fukai, M. Togo, K. Imai, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip

T. Fukai, T. Tamura, K. Imai, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

L-C-band low-voltage BiCMOS MMICs for dual-mode cellular-LAN applications

Mohammad Madihian, Y. Kinoshita, K. Imai, 1996 .

55nm CMOS Technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement

K. Taniguchi, T. Iwamoto, K. Imai, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET

S. Shishiguchi, K. Imai, N. Kimizuka, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A robust 65-nm node CMOS technology for wide-range Vdd operation

T. Fukai, T. Tamura, M. Togo, 2003, IEEE International Electron Devices Meeting 2003.

A 100 nm node CMOS technology for practical SOC application requirement

A. Ono, K. Imai, T. Matsuda, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with p-channel access transistors

H. Toyoshima, Y. Kinoshita, M. Takada, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

ICM-an analytical inversion charge model for accurate modeling of thin gate oxide MOSFETs

Chenming Hu, K. Imai, Yuhua Cheng, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.