Ganesh S. Samudra

发表

Delay and Power Evaluation of Negative Capacitance Ferroelectric MOSFET Based on SPICE Model

Kui Yao, Yang Li, Ganesh S. Samudra, 2017, IEEE Transactions on Electron Devices.

MOS device conductance modelling technique for an accurate and efficient mixed-mode simulation of CMOS circuits

Ganesh S. Samudra, Teng Kiat Lee, 1996 .

Compact HSPICE model for IMOS device

Dennis Sylvester, Chun-Huat Heng, Yee-Chia Yeo, 2008 .

Influence of OPC features on the profile of 2D mask patterns

Thomas D Milster, Byoung Il Choi, Ganesh S. Samudra, 2002, SPIE Advanced Lithography.

Extending a GTD-based image formation technique to EUV lithography

Donis G. Flagello, Thomas D Milster, Byoung Il Choi, 2003, SPIE Advanced Lithography.

Design of integrated current sensor for lateral IGBT power devices

Yung C. Liang, Ganesh S. Samudra, V.S.S. Hor, 1998 .

Analytical modelling of high temperature characteristics on the DC responses for Schottky-gate AlGaN/GaN HEMT devices

Guo-Qiang Lo, Li Yuan, Yung C. Liang, 2013, 2013 IEEE ECCE Asia Downunder.

Exposure tool chuck flatness study and effects on lithography

Cher-Huan Tan, Moitreyee Mukherjee-Roy, Ganesh S. Samudra, 2001, Microelectronic and MEMS Technologies.

Determination of LDD MOSFET drain resistance from device simulation

Ganesh S. Samudra, B. P Seah, C. H. Ling, 1996 .

A simple modelling of device speed in double-gate SOI MOSFETs

Ganesh S. Samudra, K Rajendran, G. Samudra, 2000 .

Probing the ErSi1.7 Phase Formation by Micro-Raman Spectroscopy

Yee-Chia Yeo, Tsung-Yang Liow, Ganesh S. Samudra, 2007 .

A Dual BARC method for Lithography and Etch for Dual Damascene with Low K

Ganesh S. Samudra, Moitreyee Mukherjee-Roy, Vladimir N. Bliznetsov, 2003 .

Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors

Yee-Chia Yeo, Ganesh S. Samudra, Anuj Madan, 2008 .

Accurate current sensor for lateral IGBT smart power integration

Yung C. Liang, Ganesh S. Samudra, A.J.D. Lim, 2003 .

Tunable oxide-bypassed VDMOS (OBVDMOS): breaking the silicon limit for the second generation

Yung C. Liang, Ganesh S. Samudra, Xin Yang, 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

Quantitative analysis and prediction of experimental observations on quasi-static hysteretic metal–ferroelectric–metal–insulator–semiconductor FET and its dynamic behaviour based on Landau theory

Yang Li, Yong Lian, Ganesh S. Samudra, 2015 .

120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit

Shuming Xu, Yung C. Liang, Ganesh S. Samudra, 2000 .

Predictive simulation framework for boron diffused p+ layer optimization: Sensitivity analysis of boron tube diffusion process parameters of industrial n-type silicon wafer solar cells

Ganesh S. Samudra, Johnson Wong, Armin G. Aberle, 2019, Solar Energy Materials and Solar Cells.

Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization

Yee-Chia Yeo, Ganesh S. Samudra, Eng-Huat Toh, 2007 .

Strained n-Channel FinFETs Featuring In Situ Doped Silicon – Carbon ( Si 1 − y C y ) Source and Drain Stressors With High Carbon Content

Yee-Chia Yeo, Tsung-Yang Liow, Matthias Bauer, 2009 .

Theoretical Analyses of Oxide-Bypassed Superjunction Power Metal Oxide Semiconductor Field Effect Transistor Devices

Yung C. Liang, Ganesh S. Samudra, Yu Chen, 2005 .

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Ganesh S. Samudra, S Sreelal, G. Samudra, 2002 .

Practical superjunction MOSFET device performance under given process thermal cycles

Yung C. Liang, Ganesh S. Samudra, G. Samudra, 2004 .

Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors

Kah-Wee Ang, King-Jien Chui, Yee-Chia Yeo, 2005 .

Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering

Guo-Qiang Lo, Yee-Chia Yeo, Ganesh S. Samudra, 2007 .

Measurement and simulation of hot carrier degradation in PMOSFET by gate capacitance

Ganesh S. Samudra, C. H. Ling, G. Samudra, 1995 .

Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications

Yee-Chia Yeo, Ganesh S. Samudra, Eng-Huat Toh, 2008 .

A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performance

Sohan Singh Mehta, Narayanan Balasubramanian, Navab Singh, 2004 .