Ta-Hsun Yeh

Closed loop structure to prevent couplings on CMOS process

Ying-Hsi Lin, Po-Chih Wang, Hsiao-Tsung Yen, 2016, 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC).

Characterization and modeling of Asymmetric LDD MOSFET for 65nm CMOS RF Power Amplifier design

Ying-Hsi Lin, Po-Chih Wang, Yuh-Sheng Jean, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application

Wen-Kuan Yeh, Yean-Kuen Fang, Ta-Hsun Yeh, 2005 .

Implementation of RF power MOS in 0.18/spl mu/m CMOS technology for single chip solution

Chih-Wei Chen, Heng-Ming Hsu, J.Y.-C. Sun, 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

A Ku-Band Interference-Rejection CMOS Low-Noise Amplifier Using Current-Reused Stacked Common-Gate Topology

Guo-Wei Huang, Sheng-Fuh Chang, Yuh-Sheng Jean, 2007, IEEE Microwave and Wireless Components Letters.

TECHNICAL PAPERS SOLID-STATE SCIENCE AND TECHNOLOGY

Kow-Ming Chang, Shih-Wei Wang, Ta-Hsun Yeh, 2014 .

A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process

Ying-Hsi Lin, Po-Chih Wang, Chia-Jun Chang, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

The relaxation phenomena of positive charges in thin gate oxide during Fowler-Nordheim tunneling stress

Kow-Ming Chang, Ta-Hsun Yeh, Chii-Horng Li, 1998 .