Jinpyo Park

Languages and Compilers for Parallel Computing - Toc

Michael S. Hsiao, Larry Carter, Samuel P. Midkiff, 2015 .

Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling

Siddharth Garg, Diana Marculescu, Jinpyo Park, 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC

S. Kwon, Sukhwan Lim, Jihoon Bang, 2023, IEEE Journal of Solid-State Circuits.

Optimizing Video Application Design for Phase-Change RAM-Based Main Memory

Sunggu Lee, Sungjoo Yoo, Jinpyo Park, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Region-based dual bank register allocation for reduced instruction encoding Architectures

Soo-Mook Moon, Jinpyo Park, Je-Hyung Lee, 2017, Microprocess. Microsystems.

Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems

Diana Marculescu, Guangshuo Liu, Jinpyo Park, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

Optimistic register coalescing

Soo-Mook Moon, Jinpyo Park, Soo-Mook Moon, 2004, TOPL.

Optimistic register coalescing

Soo-Mook Moon, Jinpyo Park, Soo-Mook Moon, 1998, Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192).