José Luís Almada Güntzel

发表

A Domain-specific Language for Automated Fault Injection in SystemC Models

Frank Siqueira, Douglas Lohmann, Alexis Huf, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE

José Luís Almada Güntzel, André Beims Bräscher, Ismael Seidel, 2017, 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI).

An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices

José Luís Almada Güntzel, Vinicius S. Livramento, Bruno George de Moraes, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Designing a Mask Programmable Matrix for Sequential Circuits

Luigi Carro, Marcelo de Oliveira Johann, José Luís Almada Güntzel, 1999, VLSI.

Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency

José Luís Almada Güntzel, André Beims Bräscher, Ismael Seidel, 2015, 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

An analytical timing-driven algorithm for detailed placement

Guilherme Flach, Marcelo de Oliveira Johann, José Luís Almada Güntzel, 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design

José Luís Almada Güntzel, Luciano Volcan Agostini, Jucemar Monteiro, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees

José Luís Almada Güntzel, Vinicius S. Livramento, Luiz Cláudio Villar dos Santos, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

On the calculation reuse in hadamard-based SATD

José Luís Almada Güntzel, Ismael Seidel, Marcio Monteiro, 2018, 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS).

Physical design methodologies for performance predictability and manufacturability

Ricardo Reis, Fernanda Gusmão de Lima Kastensmidt, José Luís Almada Güntzel, 2004, CF '04.

A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool

Ricardo Reis, Cristiano Lazzari, José Luís Almada Güntzel, 2004, PATMOS.

Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas

José Luís Almada Güntzel, Ricardo Augusto da Luz Reis, Ricardo Reis, 2001, RITA.

On HEVC Robustness to Integer Motion Estimation Pruning

José Luís Almada Güntzel, Ismael Seidel, Luiz Henrique Cancellier, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Real-time digital modulation classification based on Support Vector Machines

José Luís Almada Güntzel, Aldebaro Klautau, Edson Sorato, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits

Ricardo Reis, Cristiano Lazzari, José Luís Almada Güntzel, 2003, VLSI-SoC.

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

Marcelo de Oliveira Johann, José Luís Almada Güntzel, Vinicius S. Livramento, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency

José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos, Daniel P. Volpato, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Exploiting non-critical Steiner tree branches for post-placement timing optimization

José Luís Almada Güntzel, Vinicius S. Livramento, Luiz Cláudio Villar dos Santos, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Block matching hardware architecture for SATD-based successive elimination

José Luís Almada Güntzel, Ismael Seidel, Luiz Henrique Cancellier, 2017, 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI).

Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis

Ricardo Reis, José Luís Almada Güntzel, Daniel Lima Ferrão, 2006, PATMOS.

Cache-tuning-aware scratchpad allocation from binaries

José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos, Daniel P. Volpato, 2011, SBCCI '11.

High throughput architecture for H.264/AVC forward transforms block

Sergio Bampi, Ivan Saraiva Silva, José Luís Almada Güntzel, 2006, GLSVLSI '06.

A transistor sizing method applied to an automatic layout generation tool

Ricardo Reis, Cristiano Lazzari, José Luís Almada Güntzel, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms

José Luís Almada Güntzel, Vinicius S. Livramento, Bruno George de Moraes, 2011, SBCCI '11.

Mapping Data and Code into Scratchpads from Relocatable Binaries

José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos, Daniel P. Volpato, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

Clock-Tree-Aware Incremental Timing-Driven Placement

José Luís Almada Güntzel, Vinicius S. Livramento, Luiz Cláudio Villar dos Santos, 2016, ACM Trans. Design Autom. Electr. Syst..

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

José Luís Almada Güntzel, Vinicius S. Livramento, Luiz Cláudio Villar dos Santos, 2015, ISPD.

Guest Editors' Introduction: SBCCI 2018

José Luís Almada Güntzel, Michael Hübner, 2020, IEEE Des. Test.

Exploiting parallelism to speed up circuit legalization

Laércio Lima Pilla, José Luís Almada Güntzel, Márcio Bastos Castro, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Quality assessment of subsampling patterns for pel decimation targeting high definition video

José Luís Almada Güntzel, Ismael Seidel, Bruno George de Moraes, 2013, 2013 IEEE International Conference on Multimedia and Expo (ICME).

How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization

Laércio Lima Pilla, José Luís Almada Güntzel, Vinicius S. Livramento, 2019, ISPD.

Incremental timing optimization for automatic layout generation

Ricardo Reis, José Luís Almada Güntzel, Cristiano Santos, 2005, 2005 IEEE International Symposium on Circuits and Systems.

How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library

Laércio Lima Pilla, José Luís Almada Güntzel, Vinicius S. Livramento, 2017, ISPD.

Evaluating the impact of circuit legalization on incremental optimization techniques

José Luís Almada Güntzel, Vinicius S. Livramento, Luiz Cláudio Villar dos Santos, 2016, 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI).

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Marcelo de Oliveira Johann, José Luís Almada Güntzel, Vinicius S. Livramento, 2014, ACM Trans. Design Autom. Electr. Syst..

Exploiting cache locality to speedup register clustering

Laércio Lima Pilla, José Luís Almada Güntzel, Vinicius S. Livramento, 2017, 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI).

Squarer exploration for energy-efficient sum of squared differences

José Luís Almada Güntzel, Luciano Volcan Agostini, Ismael Seidel, 2016, 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS).

On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation

José Luís Almada Güntzel, André Beims Bräscher, Ismael Seidel, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Energy-efficient Hadamard-based SATD architectures

José Luís Almada Güntzel, André Beims Bräscher, Ismael Seidel, 2014, 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI).

RIC Fast Adder and its Set-Tolerant Implementation in FPGAs

José Luís Almada Güntzel, Luciano Volcan Agostini, Eduardo Mesquita, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Enhancing Multi-Threaded Legalization Through $k$-d Tree Circuit Partitioning

Laércio Lima Pilla, José Luís Almada Güntzel, Vinicius S. Livramento, 2018, 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI).

Rate-constrained successive elimination of Hadamard-based SATDs

José Luís Almada Güntzel, Luciano Volcan Agostini, Ismael Seidel, 2016, 2016 IEEE International Conference on Image Processing (ICIP).

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits

José Luís Almada Güntzel, Gustavo Wilke, Jorge Juan-Chico, 2003, PATMOS.

A New Macro-cell Generation Strategy for three metal layer CMOS Technologies

Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Augusto da Luz Reis, 2003, VLSI-SOC.

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard

Sergio Bampi, Ivan Saraiva Silva, José Luís Almada Güntzel, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Coding- and Energy-Efficient FME Hardware Design

José Luís Almada Güntzel, Luciano Volcan Agostini, Ismael Seidel, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective

José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos, Rafael Westphal, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Energy-efficient SATD for beyond HEVC

José Luís Almada Güntzel, Luciano Volcan Agostini, André Beims Bräscher, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Fast and efficient Lagrangian Relaxation-based Discrete Gate Sizing

Marcelo de Oliveira Johann, José Luís Almada Güntzel, Vinicius S. Livramento, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Coarse grain partial distortion elimination for Hadamard ME in HEVC

José Luís Almada Güntzel, Luciano Volcan Agostini, Ismael Seidel, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Relying on a Rate Constraint to Reduce Motion Estimation Complexity

Mateus Grellert, José Luís Almada Güntzel, Ismael Seidel, 2021, ICASSP 2021 - 2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders

Mateus Grellert, Cristina Meinhardt, José Luís Almada Güntzel, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

ILP-Based Global Routing Optimization with Cell Movements

David T. Westwick, José Luís Almada Güntzel, Laleh Behjat, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Comparison of 90 nm and 65 nm Logic Synthesis of a SAD Configurable VLSI Architecture

José Luís Almada Güntzel, André Beims Bräscher, Bruno George de Moraes, 2013 .

A Comparison Between High Throughput Configurable FFT / IFFT Processors

José Luís Almada Güntzel, R. Netto, P. Michel, 2012 .

TRANSIENT FAULT-TOLERANT FAST ADDERS IMPLEMENTED IN FPGAS 1

José Luís Almada Güntzel, L. Agostini, G. Corrêa, 2008 .

Autoencoder Model Exploration for Multi-Layer Video Compression

José Luís Almada Güntzel, Luiz Henrique Cancellier, Luís A. da Silva Cruz, 2022, 2022 10th European Workshop on Visual Information Processing (EUVIP).

SAD or SATD? How the Distortion Metric Impacts a Fractional Motion Estimation VLSI Architecture

José Luís Almada Güntzel, Vanio Rodrigues Filho, L. Agostini, 2021, 2021 IEEE 23rd International Workshop on Multimedia Signal Processing (MMSP).

Standalone Rate-Distortion FME Architecture

Mateus Grellert, José Luís Almada Güntzel, Ismael Seidel, 2020, 2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI).

Towards optimal use of pel decimation to trade off quality for energy

José Luís Almada Güntzel, André Beims Bräscher, Ismael Seidel, 2015, Analog Integrated Circuits and Signal Processing.

Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning

Laércio Lima Pilla, José Luís Almada Güntzel, Vinicius S. Livramento, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ILP-Based Global Routing Optimization with Cell Movements

José Luís Almada Güntzel, Aysa Fakheri Tabrizi, D. Westwick, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

E-RVP: An Initial Design Rule Violation Predictor Using Placement Information

José Luís Almada Güntzel, Aysa Fakheri Tabrizi, L. Behjat, 2022, 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Improving critical path identification in functional timing analysis

José Luís Almada Güntzel, Gustavo Wilke, Ricardo Reis, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

An improved path enumeration method considering different fall and rise gate delays

Ricardo Reis, José Luís Almada Güntzel, Fernando Moraes, 1998, Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216).