Hiroaki Kunieda

发表

A new methodology for low delay real-time videophone software architecture design

Trio Adiono, Tsuyoshi Isshiki, Dongju Li, 2002, Asia-Pacific Conference on Circuits and Systems.

Design of an efficient ASIP-based processor for object detection using AdaBoost algorithm

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2016, 2016 7th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES).

C-based RTL design method for circuit switched network on chips

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015, 2015 6th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES).

HOG-Based Object Detection Processor Design Using ASIP Methodology

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Retargeting Derivative-ASIP with Assembly Converter Tool

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2014, IEICE Trans. Inf. Syst..

Routability Analysis of Bit-Serial Pipeline Datapaths (Special Section on VLSI Design and CAD Algorithms)

Tsuyoshi Isshiki, Hiroaki Kunieda, Wayne Wei-Ming Dai, 1997 .

A Low-Cost and Energy-Efficient Multiprocessor System-on-Chip for UWB MAC Layer

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, IEICE Trans. Inf. Syst..

An Approach to Interpolated FIR Filters Based on the Cyclotomic Polynomials

Hisakazu Kikuchi, Hiroaki Kunieda, Yoshito Abe, 1986 .

Instruction Sequence Based Synthesis for Application Specific Micro-Architecture (Special Section of Papers Selected from ITC-CSCC'96)

Tsuyoshi Isshiki, Hiroaki Kunieda, Jang Kyung-Sik, 1997 .

Feature selection experiments on emotional speech classification

Hiroaki Kunieda, Thanaruk Theeramunkong, Chai Wutiwiwatchai, 2015, 2015 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).

New FPGA architecture for bit-serial pipeline datapath

Tsuyoshi Isshiki, Hiroaki Kunieda, Akihisa Ohta, 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

A hybrid method for fingerprint image quality calculation

Dongju Li, Hiroaki Kunieda, Jinqing Qi, 2005, Fourth IEEE Workshop on Automatic Identification Advanced Technologies (AutoID'05).

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

VLSI system compiler for digital signal processing: modularization and synchronization

Hiroaki Kunieda, K. Itoh, 1990, IEEE International Symposium on Circuits and Systems.

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2010, 2010 Fourth IEEE International Conference on Biometrics: Theory, Applications and Systems (BTAS).

Entropy Decoding Processor for Modern Multimedia Applications

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

RHINE: Reconfigurable Multiprocessor System for Video CODEC (Special Section on JTC-CSCC '92)

Yoshinori Takeuchi, Hiroaki Kunieda, Zhao-Chen Huang, 1993 .

Code Generation Problem for Digital Signal processors

Hiroaki Kunieda, Norichika Kumamoto, 1988 .

A new high logic density FPGA for bit-serial pipeline datapath

Tsuyoshi Isshiki, Hiroaki Kunieda, A. Ohta, 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

Realization of fingerprint identification module on DSP board

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2002, Asia-Pacific Conference on Circuits and Systems.

Hierarchical circuit optimization for analog LSIs using device model refining

Hiroaki Kunieda, Tomohiko Ohtsuka, 1994, Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems.

New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec

Trio Adiono, Tsuyoshi Isshiki, Dongju Li, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A design method for real-time image denoising circuit using High-Level Synthesis

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2016, 2016 7th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES).

A Reconfigurable High Performance ASIP Engine for Image Signal Processing

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

Ultra fast fingerprint indexing for embedded system

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2010, 2010 International Conference of Soft Computing and Pattern Recognition.

The lmprovement in Performance-Driven Analog LSI Layout System LIBRA

Hiroaki Kunieda, Nobuyuki Kurosawa, Tomohiko Ohtsuka, 1993 .

A Cost-Effective Network for Very Large ATM Cross-Connects : The Delta Network with Expanded Middle Stages (Special Issue on Distributed Architecture for Next Generation Communication Networks)

Hiroaki Kunieda, Takashi Shimizu, 1994 .

A new FPGA architecture for high-performance bit-serial pipeline datapath (abstract)

Tsuyoshi Isshiki, Hiroaki Kunieda, Akihisa Ohta, 1998, FPGA '98.

Face focus coding under H.263+ video coding standard

Trio Adiono, Tsuyoshi Isshiki, Dongju Li, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Dalvik bytecode acceleration using Fetch/Decode Hardware Extension with hybrid Execution

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Cost-effective shadowing method using the ED-buffer on an adaptive light cube

Tsuyoshi Isshiki, Hiroaki Kunieda, Makoto Ishikawa, 2000, The Visual Computer.

Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015, J. Inf. Process..

Ultrafast fingerprint indexing for embedded systems

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2011 .

Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

Fingerprint verification with scratch feature for personal portable devices

Dongju Li, Hiroaki Kunieda, SangWoo Sin, 2012 .

Motion estimator LSI for MPEG2 high level standard

Dongju Li, Hiroaki Kunieda, Li Jiang, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Robust Multiple Minutiae Partitions for Fingerprint Authentication

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, 2012 International Symposium on Biometrics and Security Technologies.

Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

are-Software C

Hiroaki Kunieda, 1996 .

Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Graph (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)

Yoshinori Takeuchi, Tsuyoshi Isshiki, Hiroaki Kunieda, 1993 .

Efficient Synchronization for Distributed Embedded Multiprocessors

Ning Wu, Yuangang Wang, Jun Xu, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

VIRGO: hierarchical DSP code generator based on vectorized signal flow graph description

Hiroaki Kunieda, Keiji Aoki, Norichika Kumamoto, 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC

Tsuyoshi Isshiki, Hiroaki Kunieda, Hao Xiao, 2012, 2012 IEEE International Conference on Consumer Electronics (ICCE).

Array architecture and design for image window operation processing ASICs

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Parallel processor scheduling for digital signal processing

Hiroaki Kunieda, S. Toyoshima, 1989, IEEE International Symposium on Circuits and Systems,.

Fingerprint spoof detection using wavelet based local binary pattern

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2017, International Conference on Graphic and Image Processing.

Space Partitioning Image Processing Technique for Parallel Recursive Half Toning

Yoshinori Takeuchi, Hiroaki Kunieda, 1993 .

New VLSI array processor design for image window operations

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 1999 .

Efficient anti-aliasing algorithm for computer generated images

Tsuyoshi Isshiki, Hiroaki Kunieda, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

VLSI system compiler for digital signal processing: Extended modularization and placement

T. Shimizu, Hiroaki Kunieda, K. Ito, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

High speed bit-serial parallel processing on array architecture

Hiroaki Kunieda, Kazuhito Ito, Takenobu Shimizugashira, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Application-specific Instruction-Set Processor design methodology for wireless image transmission systems

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, 2012 International SoC Design Conference (ISOCC).

Automatic design for bit-serial MSPA architecture

Dongju Li, Hiroaki Kunieda, Kazuhito Ito, 1995, ASP-DAC '95.

A reconfigurable ASIP-based approach for high performance image signal processing

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Novel Fingerprint SoC with Bit Serial FPGA Engine (特集:システムLSIの設計技術と設計自動化)

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2005 .

Design Optimization of VLSI Array Processor Architecture for Window Image Processing (Special Section on Digital Signal Processing)

Dongju Li, Hiroaki Kunieda, Li Jiang, 1999 .

H.264/AVC decoder SoC towards the low cost mobile video player

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2007, 2007 IEEE International SOC Conference.

A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2014, J. Inf. Process..

Fingerprint authentication on touch sensor using Phase-Only Correlation method

Tsuyoshi Isshiki, Hiroaki Kunieda, Nabilah Shabrina, 2016, 2016 7th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES).

Online Traffic Information Retrieving for a Driver using Speech Recognition including Enhancement Methods

Hiroaki Kunieda, Chai Wutiwiwatchai, Pakinee Aimmanee, 2012 .

Parallel Processing for Bilateral Two Dimensional Filters

Yoshinori Takeuchi, Hiroaki Kunieda, 1989 .

An efficient embedded processor for object detection using ASIP methodology

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2016, 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2013, J. Inf. Process..

Custom instruction search for application specific instruction-set processor using guided simulated annealing

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm(Special Section on Digital Signal Processing)

Dongju Li, Hiroaki Kunieda, Li Jiang, 1998 .

An optimal scheduling method for parallel processing system of array architecture

Hiroaki Kunieda, Kazuhito Ito, T. Iwata, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Orientation Field Estimation for Embedded Fingerprint Authentication System

Wei Tang, Tsuyoshi Isshiki, Dongju Li, 2010, IEICE Trans. Inf. Syst..

Trace-driven workload simulation method for Multiprocessor System-On-Chips

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2009, 2009 46th ACM/IEEE Design Automation Conference.

A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic Modeling for Contention Stall in A Priority Based MPSoC Bus

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2016, IPSJ Trans. Syst. LSI Des. Methodol..

Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2011, IEICE Trans. Inf. Syst..

High-Level Synthesis for Array Architecture Digital Signal Processing Systems

Hiroaki Kunieda, Kazuhito Ito, Tadashi Iwata, 1996 .

CPU core generation for hardware-software codesign

Hiroaki Kunieda, Kyung-Sik Jang, 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

Efficient method for face region quality enhancement in low bit rate video coding

Trio Adiono, Tsuyoshi Isshiki, Dongju Li, 2002, Asia-Pacific Conference on Circuits and Systems.

A Parallel Implementation for Digital Half Toning

Yoshinori Takeuchi, Hiroaki Kunieda, 1991 .

Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer

Tsuyoshi Isshiki, Hiroaki Kunieda, Hao Xiao, 2017, IET Comput. Digit. Tech..

An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification

Hans G. Kerkhoff, Trio Adiono, Hiroaki Kunieda, 2009 .

Bit-serial pipeline synthesis and layout for large-scale configurable systems

Tsuyoshi Isshiki, Hiroaki Kunieda, Wayne Wei-Ming Dai, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

High density bit-serial FPGA with LUT embedding shift register function

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2002, Asia-Pacific Conference on Circuits and Systems.

Branch bitstream [Machine Instruction-level System Tracing]

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015, 2015 6th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES).

Distributed synchronization for message-passing based embedded multiprocessors

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2014, 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors.

FPGA for high-performance bit-serial pipeline datapath

Tsuyoshi Isshiki, Hiroaki Kunieda, Akihisa Ohta, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

System-MSPA design of H.263+ video encoder LSI for face focused videotelephony

Trio Adiono, Tsuyoshi Isshiki, Dongju Li, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Towards one chip HDTV MPEG2 encoder LSI

Dongju Li, Hiroaki Kunieda, Li Jiang, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Modularization and Processor Placement for DSP Neo-Systolic Array (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)

Hiroaki Kunieda, Kazuhito Ito, Takashi Shimizu, 1993 .

A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

New Macroblock Engine Architecture for Video Processing

Trio Adiono, Dongju Li, Hiroaki Kunieda, 2005, MVA.

LIBRA: Automatic Performance-Driven Layout for Analog LSIs

Hiroaki Kunieda, Mineo Kaneko, Tomohiko Ohtsuka, 1992 .

MAPS: An integrated framework for MPSoC application parallelization

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2008, 2008 45th ACM/IEEE Design Automation Conference.

RECONFIGURABLE MULTIPROCESSOR SYSTEM RHINE FOR MOVING PICTURE CODEC

Yoshinori Takeuchi, Hiroaki Kunieda, Masatomo Saeki, 1992 .

System-Level VLSI Design

Hiroaki Kunieda, 2016 .

Narrow Fingerprint Template Synthesis by Clustering Minutiae Descriptors

Zhiqiang Hu, Tsuyoshi Isshiki, Dongju Li, 2017, IEICE Trans. Inf. Syst..

Hybrid Minutiae Descriptor for Narrow Fingerprint Verification

Zhiqiang Hu, Tsuyoshi Isshiki, Dongju Li, 2017, IEICE Trans. Inf. Syst..

Narrow Fingerprint Sensor Verification with Template Updating Technique

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 2D-FFT ALGORITHM ON MESH CONNECTED MULTIPROCESSOR SYSTEMS

Hiroaki Kunieda, Kazuhito Itoh, 1987 .

Unique Fingerprint-Image-Generation Algorithm for Line Sensors

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multi-camera based human localization for room utilization monitoring system

Hiroaki Kunieda, Ithipan Methasate, Issariyapol Siriwat, 2014, 2014 11th International Joint Conference on Computer Science and Software Engineering (JCSSE).

A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Distributed Load Balancing Schemes for Parallel Video Encoding System

Yoshinori Takeuchi, Hiroaki Kunieda, Zhao-Chen Huang, 1994 .

SIFT-based algorithm for fingerprint authentication on smartphone

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015, 2015 6th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES).

Bridging the Gap between ASIC and GPP: A High-Performance and C-Programmable ASIP for Image Processing

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2012 .

H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method

Trio Adiono, Tsuyoshi Isshiki, Dongju Li, 2001, ISAS-SCI.

An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification

Hans G. Kerkhoff, Trio Adiono, Hiroaki Kunieda, 2009 .

Topological Transformation for Application-Specific Instruction-Set Processor Datapath Synthesis

Hiroaki Kunieda, Kyung Sik Jang, 1996 .

Online Detection of Spoof Fingers for Smartphone-Based Applications

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

Two dimensional space segmentation recursive filtering algorithm on rectangular processor array

Hiroaki Kunieda, Y. Takeuchi, 1990, IEEE International Symposium on Circuits and Systems.

A Parallel Image Compression Algorithm Using Space Partitioning Wavelet Transform

Yoshinori Takeuchi, Hiroaki Kunieda, Tatsuyuki Negishi, 1993 .

Effective processor array architecture with shared memory

Hiroaki Kunieda, K. Hagiwara, 1994, Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems.

C-Based RTL Design Framework for Processor and Hardware-IP Synthesis

Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, 2015 .

RHINE: Reconfigurable Multiprocessor System for Video CODEC

Hiroaki Kunieda, Zhao-Chen Huang, Yoshinori Takeuchi, 1993 .

Scalable VLSI architectures for lattice structure-based discrete wavelet transform

Tsuyoshi Isshiki, Hiroaki Kunieda, Yong Hoon Lee, 1998 .