K. Akita

A 50-nm 1.2-V GexTe1−x/Sb2Te3 superlattice topological-switching random-access memory (TRAM)

T. Morikawa, K. Shiraishi, M. Araidai, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Fabrication process for pillar GeTe/Sb2Te3 superlattice topological-switching random access memory

T. Morikawa, M. Kinoshita, N. Takaura, 2015 .

55-µA GexTe1−x/Sb2Te3 superlattice topological-switching random access memory (TRAM) and study of atomic arrangement in Ge-Te and Sb-Te structures

T. Morikawa, K. Shiraishi, J. Tominaga, 2014, 2014 IEEE International Electron Devices Meeting.

Superlattice Phase Change Memory Fabrication Process for Back End of Line Devices

Norikatsu Takaura, T. Morikawa, J. Tominaga, 2013 .