P. Su

Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device

Tahui Wang, Kai-Shin Li, Chao-Cheng Lin, 2020, IEEE Transactions on Electron Devices.

Modeling of Read-Disturb-Induced SET-State Current Degradation in a Tungsten Oxide Resistive Switching Memory

Tahui Wang, Cheng-Min Jiang, P. Su, 2018, IEEE Electron Device Letters.

Characterization and modeling of SET/RESET cycling induced read-disturb failure time degradation in a resistive switching memory

Tahui Wang, P. Su, Chun Chi Hsu, 2017 .

A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS2 FET

C. Hu, W. Yeh, Tahui Wang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Yao-Jen Lee, C. Hu, W. Yeh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory

Po-Cheng Su, Wen-Jie Lin, Tahui Wang, 2016, IEEE Transactions on Electron Devices.

Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory

Chih-Yuan Lu, Tahui Wang, Min-Cheng Chen, 2015, IEEE Electron Device Letters.