F. Hirler

A New Fast and Rugged 100 V Power MOSFET

R. Siemieniec, F. Hirler, A. Schlogl, 2006, 2006 12th International Power Electronics and Motion Control Conference.

Optimizing the vertical IGBT structure-the NPT concept as the most economic and electrically ideal solution for a 1200 V-IGBT

T. Laska, W. Scholz, F. Hirler, 1996, 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings.

Design of avalanche capability of Power MOSFETs by device simulation

I. Pawel, R. Siemieniec, F. Hirler, 2007, 2007 European Conference on Power Electronics and Applications.

A new robust power MOSFET family in the voltage range 80 V-150 V with superior low R/sub Dson/, excellent switching properties and improved body diode

R. Siemieniec, F. Hirler, M. Rosch, 2005, 2005 European Conference on Power Electronics and Applications.

1200 V-trench-IGBT study with square short circuit SOA

T. Laska, T. Schmidt, F. Hirler, 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

Space-saving edge-termination structures for vertical charge compensation devices

R. Siemieniec, F. Hirler, C. Geissler, 2009, 2009 13th European Conference on Power Electronics and Applications.

Failure of multiple-cell power DMOS transistors in avalanche operation

G. Wachutka, J. Krumrey, R. Henninger, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Simulating the Avalanche Behavior of Trench Power MOSFETs

R. Herzer, I. Pawel, R. Siemieniec, 2006 .

Failure mechanism of power DMOS transistors under UIS stress conditions

G. Wachutka, J. Krumrey, F. Hirler, 2002, The Fourth International Conference on Advanced Semiconductor Devices and Microsystem.

UIS-Failure of DMOS Power Transistors

G. Wachutka, J. Krumrey, F. Hirler, 2002, 32nd European Solid-State Device Research Conference.