A. Pal

Impact of runtime leakage reduction techniques on delay and power sensitivity under effective channel length variations

S. Roy, A. Pal, 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

HotSpot minimization using fine-grained DVS architecture at 90 nm technology

R. Mukherjee, P. Ghosh, A. Pal, 2012, 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics.

A novel approach for the identification of totally symmetric Boolean functions in the application of efficient system design

A. Tiwari, A. Pal, G. Paul, 2008, 2008 3rd International Design and Test Workshop.

A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing and Wavelength Assignment in Optical WDM Networks

I. Sengupta, T. De, A. Pal, 2008, 2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems.

Artificial intelligence approach to test vector reordering for dynamic power reduction during VLSI testing

I. Sen Gupta, S. Roy, A. Pal, 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers

A. Pal, B.B. Bhattacharya, G. Paul, 2006, 2006 International Conference on Electrical and Computer Engineering.

Methodology for thermal aware physical design

A. Pal, P. Agrawal, V.P. Kalangi, 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

Power-delay efficient technology mapping of BDD-based circuits using DCVSPG cells

A. Pal, B.B. Bhattacharya, G. Paul, 2008, 2008 3rd International Design and Test Workshop.

Multicues Face Detection in Complex Background for Frontal Faces

A. Pal, A. Pal, 2008, 2008 International Machine Vision and Image Processing Conference.

Low power design of on-line testers for digital circuits using state encoding

A. Pal, G. Paul, C.R. Mandal, 2008, 2008 3rd International Design and Test Workshop.

A four-variable programmable universal logic module using digital summation threshold logic gates

A. Pal, 1984, Proceedings of the IEEE.