J. Korenek

发表

volutionary circuit design for fast FPGA-based classification of etwork application protocols

M. Zádník, L. Sekanina, J. Korenek, 2015 .

Enabling Event-Triggered Data Plane Monitoring

Diana Andreea Popescu, Han Wang, Gianni Antichi, 2020, SOSR.

Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs

Lukás Sekanina, Jan Korenek, L. Sekanina, 2005, ICES.

High-speed regular expression matching with pipelined automata

Jan Korenek, Denis Matousek, Viktor Pus, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing

Jan Korenek, Jan Kastil, J. Korenek, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Packet header analysis and field extraction for multigigabit networks

Jan Korenek, Libor Polcak, Petr Kobierský, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis

Jan Korenek, Roman Vrána, R. Vrána, 2021, 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Line rate programmable packet processing in 100Gb networks

Jan Korenek, Pavel Benácek, Viktor Pus, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution

Jirí Matousek, Andrew W. Moore, Jan Korenek, 2017, 2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

Software Defined Monitoring of Application Protocols

Athanasios V. Vasilakos, Jan Korenek, Viktor Pus, 2016, IEEE Transactions on Computers.

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring

Jan Korenek, Pavel Benácek, Viktor Pus, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era

G. Antichi, David Janecek, J. Korenek, 2022, IEEE/ACM Transactions on Networking.

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Jan Korenek, Pavel Benácek, Viktor Pus, 2018, FPGA.

Mapping of P4 match action tables to FPGA

Jan Korenek, Michal Kekely, J. Korenek, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Hardware accelerated flow measurement of 100 Gb ethernet

Jan Korenek, Viktor Pus, Petr Velan, 2015, 2015 IFIP/IEEE International Symposium on Integrated Network Management (IM).

Low-latency modular packet header parser for FPGA

Jan Korenek, Viktor Pus, Lukas Kekely, 2012, 2012 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

Hash-based Pattern Matching for High Speed Networks

Jan Korenek, Tomas Fukac, J. Korenek, 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Adaptive development of hash functions in FPGA-based network routers

Lukás Sekanina, Jan Korenek, Roland Dobai, 2016, 2016 IEEE Symposium Series on Computational Intelligence (SSCI).

Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications

Jan Korenek, Roland Dobai, J. Korenek, 2015, 2015 IEEE Symposium Series on Computational Intelligence.

Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA

Jan Korenek, Vlastimil Kosar, J. Korenek, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Software Defined Monitoring of application protocols

Jan Korenek, Viktor Pus, Lukas Kekely, 2014, IEEE INFOCOM 2014 - IEEE Conference on Computer Communications.