J. Hicks

发表

Reliability versus yield and die location in deep sub-micron VLSI

W. C. Riordan, R. Miller, J. Hicks, 2000, Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130).

Aging model challenges in deeply scaled tri-gate technologies

S. Mudanai, S. Ramey, C. Prasad, 2015, 2015 IEEE International Integrated Reliability Workshop (IIRW).

Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

A. Rahman, C. Tsai, P. Bai, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Transistor Performance Impact Due to Die–Package Mechanical Stress

J. Hicks, D. Pantuso, G. S. Leatherman, 2013, IEEE Transactions on Device and Materials Reliability.

Reliability versus yield and die location in advanced VLSI

W. C. Riordan, R. Miller, J. Hicks, 1999 .

Microprocessor reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process

W. C. Riordan, R. Miller, J. Hicks, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

Die-package stress interaction impact on transistor performance

J. Xu, J. Hicks, D. Pantuso, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology

M. Jones, W. Hafez, K. Komeyli, 2010, 2010 IEEE International Reliability Physics Symposium.

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

S. Natarajan, M. Agostinelli, C. Tsai, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Intrinsic transistor reliability improvements from 22nm tri-gate technology

A. Rahman, S. Ramey, C. Auth, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Accelerated stress testing methodology to risk assess silicon-package thermomechanical failure modes resulting from moisture exposure under use condition

Jun He, Min Pei, J. Hicks, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process

C. Auth, J. Hicks, A. Schmitz, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Erratic fluctuations of sram cache vmin at the 90nm process technology node

J. Jopling, M. Jones, M. Agostinelli, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

K. Mistry, J. Hicks, P. Hentges, 2012, 2012 IEEE International Interconnect Technology Conference.

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

J. Jopling, C. Prasad, T. Ghani, 2009, 2009 IEEE International Reliability Physics Symposium.

BTI recovery in 22nm tri-gate technology

S. Ramey, J. Hicks, S. Novak, 2014, 2014 IEEE International Reliability Physics Symposium.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

J. Jopling, M. Agostinelli, C. Prasad, 2008, 2008 IEEE International Reliability Physics Symposium.

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

C. Prasad, S. Ramey, J. Hicks, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).