Christine Raynaud

发表

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec

Alexandre Valentian, Philippe Flatresse, Pascal Urard, 2011, 2011 IEEE International Solid-State Circuits Conference.

Millimeter wavedesign with65nm LPSOIHR CMOS technology

Baudouin Martineau, Francois Danneville, Gilles Dambrine, 2007 .

Intra-chip wireless interconnections based on high performances integrated antennas

Philippe Benech, C. Tinella, Olivier Richard, 2005 .

State oftheart200GHzpassive components andcircuits integrated in advanced thinSOICMOS technology onHighResistivity substrate

Daniel Gloria, Ph. Benech, S. Boret, 2006 .

High voltage devices in advanced CMOS technologies

Frederic Monsieur, Christine Raynaud, Raúl Andrés Bianchi, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Integrated Inductors inHR SOICMOS technologies: on theeconomic advantage ofSOItechnologies fortheintegration ofRFapplications

Daniel Gloria, S. Boret, S. Montusclat, 2007 .

The properties of cellulose insulation applied via the wet spray process

Christine Raynaud, Pablo Lopez Hurtado, Antoine Rouilly, 2016 .

65nm RFCMOStechnologies withbulkandHR SOIsubstrate for millimeter wave passives andcircuits characterized up to220GHZ

Gilles Dambrine, S. Boret, C. Clement, 2006 .

A SOl CMOS Reconfigurable Output Matching Network for

A. Giry, Grenoble Alpes, Christine Raynaud, 2015 .

65nm Low Power (LP) SOI technology on HR substrate for WLAN and Mmwave SOCs

Baudouin Martineau, Frederic Gianesello, Georges Guegan, 2009 .

A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI

Baudouin Martineau, Nicolas Deparis, Muneo Fukaishi, 2009, 2009 Proceedings of ESSCIRC.

Radio-frequency and low noise characteristics of SOI technology on plastic for flexible electronics

Emmanuel Dubois, Daniel Gloria, Francois Danneville, 2013 .

A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS

Boris Murmann, Andreia Cathelin, Christine Raynaud, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

Baudouin Martineau, Nicolas Deparis, Muneo Fukaishi, 2010, IEEE Journal of Solid-State Circuits.

Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs

Sorin Cristoloveanu, Dimitris E. Ioannou, J. Pretet, 2002 .

Kink-Related Excess Noise in Deep Submicron Partially and Moderately Fully Depleted Unibond N-Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

Sebastien Haendler, Jalal Jomaah, Christine Raynaud, 2000 .

Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing

G. Reimbold, Claire Fenouillet-Beranger, Sorin Cristoloveanu, 2004 .

65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs

Baudouin Martineau, Frederic Gianesello, Georges Guegan, 2009 .

A converging route towards very high frequency, mechanically flexible, and performance stable integrated electronics

Emmanuel Dubois, Daniel Gloria, Francois Danneville, 2013 .

Performance of Submicrometer Channel-Length

G. Guegan, J. Gautier, Gilles Dambrine, 1991 .