Chang-Kyo Lee

发表

A 550-$\mu\hbox{W}$ 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction

Sang-Hyun Cho, Jong-Kee Kwon, Seung-Tak Ryu, 2011, IEEE Journal of Solid-State Circuits.

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

Wan Kim, Seung-Tak Ryu, Chang-Kyo Lee, 2012 .

Reliable 2-bit/cell NVM technology using twin SONOS memory transistor

Byeoung-Soo Park, Byung Yong Choi, Dong Woon Kim, 2005 .

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

Jae-Joon Song, Kyung-Soo Kim, Jongmin Kim, 2018, 2018 IEEE Symposium on VLSI Circuits.

A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design

Wan Kim, Seung-Tak Ryu, Hyun-Wook Kang, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

Junha Lee, Jung-Hwan Choi, Joon-Young Park, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction

Sang-Hyun Cho, Jong-Kee Kwon, Seung-Tak Ryu, 2010, IEEE Custom Integrated Circuits Conference 2010.

A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

Ho-Jin Park, Choong-Hoon Lee, Jong-In Kim, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Design of a 1-Volt and μ-power SARADC for Sensor Network Application

Sang-Hyun Cho, Jong-In Song, Chang-Kyo Lee, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm

Sang-Gug Lee, Sang-Hyun Cho, Seung-Tak Ryu, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

Jongmin Kim, Jung-Hwan Choi, Joon-Young Park, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

An LDO-based supply referencing 10b 32MS/s pipelined ADC

Ji-Wook Kwon, Seung-Tak Ryu, Chang-Kyo Lee, 2011, 2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals.

A time-interleaved flash-SAR architecture for high speed A/D conversion

Sang-Hyun Cho, Jong-In Kim, Seung-Tak Ryu, 2009, 2009 IEEE International Symposium on Circuits and Systems.

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Jonghyuk Kim, Hoon Lee, Young Choi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications

Seung-Tak Ryu, Chang-Kyo Lee, Ghil-Geun Oh, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

Real-time 3D human pose recognition from reconstructed volume via voxel classifiers

Wonjun Kim, Du-Sik Park, Junmo Kim, 2014, Electronic Imaging.

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

Dongkeon Lee, Dukha Park, Byongwook Na, 2020, IEEE Journal of Solid-State Circuits.

Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC

Seung-Tak Ryu, Chang-Kyo Lee, 2019, IET Circuits Devices Syst..

Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments

Soo-Hyun Cho, Sung-Hun Lee, Wan-Jin Ko, 2018, ICUFN.

Digital error correction technique for binary decision successive approximation ADCs

Seung-Tak Ryu, Chang-Kyo Lee, Ba-Ro-Saim Sung, 2009 .