K.L. Cheng

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

C.C. Chen, H.J. Tao, C.H. Diaz, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

C.C. Chen, C.H. Wang, Y.K. Leung, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..