Jerrell P. Hein

DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures

Jerrell P. Hein, Mike Petrowski, 2005 .

An EPR4 read/write channel with digital timing recovery

Li Du, German S. Feyh, Trent Dudley, 1998 .

Utilizing a Hybrid Analog/Digital Loop Filter

Ligang Zhang, Yunteng Huang, Michael H. Perrott, 2006 .

THAM 11.3: A Single-Chip Digital Signaling Interface for the DSI lntraoffice Environment

Jerrell P. Hein, Richard J. Starke, 1989 .

2 A 2 . 5 Gb / s Multi-Rate 0 . 25 μ m CMOS CDR Utilizing a Hybrid Analog / Digital Loop Filter

Jerrell P. Hein, Bruno W. Garlepp, Perrott, 2000 .