Paul Chow

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Maximizing system performance: using reconfigurability to monitor system communications

Lesley Shannon, Paul Chow, P. Chow, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009

Paul Chow, Peter Y. K. Cheung, P. Chow, 2009, Symposium on Field Programmable Gate Arrays.

Accelerating Apache Spark with FPGAs

Paul Chow, Ehsan Ghasemi, 2019, Concurr. Comput. Pract. Exp..

Sonar: Writing Testbenches through Python

Varun Sharma, Paul Chow, Naif Tarafdar, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method

Jiang Jiang, Yuan Li, Minxuan Zhang, 2012, 2012 International Conference on Field-Programmable Technology.

Memory interfacing and instruction specification for reconfigurable processors

Paul Chow, Jeffrey A. Jacob, P. Chow, 1999, FPGA '99.

Integrating High-Level Synthesis into MPI

Paul Chow, Andrew W. H. House, Manuel Saldaña, 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy

Lothar Lilge, Jason Luu, Jonathan Rose, 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI

Paul Chow, Charles Lo, 2011, FPGA '11.

The Transmogrifier-2: a 1 million gate rapid-prototyping system

Jonathan Rose, Paul Chow, David M. Lewis, 1998, IEEE Trans. Very Large Scale Integr. Syst..

A Software Parallel Programming Approach to FPGA-Accelerated Computing pdf

Ruediger Willenberg, Paul Chow, 2014, ArXiv.

The routability of multiprocessor network topologies in FPGAs

Lesley Shannon, Paul Chow, Manuel Saldaña, 2006, FPGA '06.

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

Jonathan Rose, Paul Chow, David Lewis, 1990 .

A multi-FPGA architecture for stochastic Restricted Boltzmann Machines

Paul Chow, Daniel Le Ly, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method

Jiang Jiang, Yuan Li, Minxuan Zhang, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

SimXMD: Simulation-based HW/SW co-debugging

Ruediger Willenberg, Paul Chow, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse

Lesley Shannon, Paul Chow, P. Chow, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs

Paul Chow, Daniel Rozhko, 2019, FPGA.

Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation

Paul Chow, Tor M. Aamodt, 2000, CASES '00.

SimXMD: Integrated debugging of C code and hardware components

Ruediger Willenberg, Paul Chow, 2012, 2012 International Conference on Field-Programmable Technology.

FPGA-based training of convolutional neural networks with a reduced precision floating-point library

Lin Sun, Paul Chow, Roberto DiCecco, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Exploiting dual data-memory banks in digital signal processors

Paul Chow, Mazen A. R. Saghir, Corinna G. Lee, 1996, ASPLOS VII.

NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract

Paul Chow, J. Gregory Steffan, Stuart Byma, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Application-driven design of DSP architectures and compilers

Paul Chow, Mazen A. R. Saghir, Corinna G. Lee, 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.

Integrating FPGAs in high-performance computing: introduction

Paul Chow, Mike Hutton, 2007, FPGA '07.

On-Chip Instruction Caches for High Performance Processors,

Anant Agarwal, Paul Chow, Mark Horowitz, 1987 .

Building the Reconfigurable Cloud Ecosystem

Paul Chow, 2017, ETCD@ASPLOS.

Simplifying the integration of processing elements in computing systems using a programmable controller

Lesley Shannon, Paul Chow, P. Chow, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache

Anant Agarwal, Paul Chow, John L. Hennessy, 1987 .

RACER: a reconfigurable constraint-length 14 Viterbi decoder

Paul Chow, Gennady Feygin, David Yeh, 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems

Paul Chow, Manuel Saldaña, Emanuel Ramalho, 2009, Int. J. Reconfigurable Comput..

A profiler for a heterogeneous multi-core multi-FPGA system

Paul Chow, Manuel Saldaña, Daniel Nunes, 2008, 2008 International Conference on Field-Programmable Technology.

Exploring pipe implementations using an OpenCL framework for FPGAs

Paul Chow, Vincent Mirian, 2015, 2015 International Conference on Field Programmable Technology (FPT).

GENERALIZED CASCADE VITERBI DECODER - WITH LINEAR SPEED-UP

Paul Chow, G. Feygin, Patrick Glenn Gulak, 1991 .

Leveraging reconfigurability in the hardware/software codesign process

Lesley Shannon, Paul Chow, 2011, TRETS.

A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI

Paul Chow, Manuel Saldaña, Emanuel Ramalho, 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition

Paul Chow, Jianfeng Zhang, Hengzhu Liu, 2015, ACM Trans. Reconfigurable Technol. Syst..

Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy

Paul Chow, Tor M. Aamodt, P. Chow, 2008, TECS.

A Pipelined Distributed Arithmetic PFFT Processor

Paul Chow, Zvonko G. Vranesic, J. L. Yen, 1983, IEEE Transactions on Computers.

Task replication and control for highly parallel in-memory stores

Paul Chow, Fernando Martin del Campo, 2017, MEMSYS.

Hardware acceleration of a Monte Carlo simulation for photodynamic therapy [corrected] treatment planning.

Lothar Lilge, Jason Luu, Paul Chow, 2009, Journal of biomedical optics.

Using Partial Reconfiguration in an Embedded Message-Passing System

Paul Chow, Manuel Saldaña, Hao Jun Liu, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

MPack: global memory optimization for stream applications in high-level synthesis

Paul Chow, Jasmina Vasiljevic, 2014, FPGA.

Using an OpenCL framework to evaluate interconnect implementations on FPGAs

Paul Chow, Vincent Mirian, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC

Paul Chow, Jianfeng Zhang, Hengzhu Liu, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

K-means implementation on FPGA for high-dimensional data using triangle inequality

Paul Chow, Charles Lo, Zhongduo Lin, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

A Hardware Overview

Paul Chow, 1989 .

A Message from the General Chair and Program Chair

Paul Chow, Satnam Satnam, 2012, FCCM 2012.

A Comparison of Traditional and VLIW DSP Architectures for Compiled DSP Applications

Paul Chow, Mazen A. R. Saghir, Corinna G. Lee, 2003 .

FPGA acceleration of Monte-Carlo based credit derivative pricing

Paul Chow, Alexander Kaganov, Asif Lakhany, 2008, 2008 International Conference on Field Programmable Logic and Applications.

High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines

Paul Chow, Daniel Le Ly, P. Chow, 2010, IEEE Transactions on Neural Networks.

A 20 MIPS Peak Microprocessor with On-Chip Cache,

Paul Chow, John L. Hennessy, Mark Horowitz, 1984 .

Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI

Paul Chow, Manuel Saldaña, Emanuel Ramalho, 2006, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006).

A Heterogeneous GASNet Implementation for FPGA-accelerated Computing

Ruediger Willenberg, Paul Chow, 2014, PGAS.

The Predictability of Computations that Produce Unpredictable Outcomes

Andreas Moshovos, Paul Chow, Tor M. Aamodt, 2001 .

MPI as a Programming Model for High-Performance Reconfigurable Computers

Ralph Wittig, Danyao Wang, Paul Chow, 2010, TRETS.

FCache: a system for cache coherent processing on FPGAs

Paul Chow, Vincent Mirian, 2012, FPGA '12.

Memory-System Design Considerations for Dynamically-Scheduled Processors

Norman P. Jouppi, Paul Chow, Zvonko G. Vranesic, 1997, ISCA.

Using reconfigurability to achieve real-time profiling for hardware/software codesign

Lesley Shannon, Paul Chow, 2004, FPGA '04.

29. Solving non-linear electronic packaging problems on parallel computers using domain decomposition

Paul Chow, Olivier Pironneau, Tony Chan, 2001 .

Routability of Network Topologies in FPGAs

Lesley Shannon, Paul Chow, John Craig, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The Compiler System

Paul Chow, 1989 .

Architecture Exploration for Data Intensive Applications

Paul Chow, Fernando Martin del Campo, P. Chow, 2015, MEMSYS.

The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning

Norman P. Jouppi, Paul Chow, Zvonko G. Vranesic, 1999, International Journal of Parallel Programming.

A 32b microprocessor with on-chip 2Kbyte instruction cache

Steven W. K. Tjiang, Anant Agarwal, Peter Steenkiste, 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

The design and testing of MIPS-X

Mark Horowitz, Paul Chow, 1988 .

FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC

Paul Chow, Jianfeng Zhang, Hengzhu Liu, 2015, 2015 International Conference on Field Programmable Technology (FPT).

Hardware Support for Broadcast and Reduce in MPSoC

Paul Chow, Yuanxi Peng, Manuel Saldaña, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Reconfigurable molecular dynamics simulator

Paul Chow, Ian Kuon, Aaron Egier, 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding

P. Glenn Gulak, Paul Chow, Gennady Feygin, 1994, Inf. Process. Manag..

Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use

Paul Chow, Jasmina Vasiljevic, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

A streamlined DSP microprocessor architecture

Paul Chow, M. Takefman, 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

Designing an FPGA SoC using a standardized IP block interface

Samir Parikh, Lesley Shannon, Paul Chow, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

Optimization of data prefetch helper threads with path-expression based statistical modeling

Paul Chow, Tor M. Aamodt, P. Chow, 2007, ICS '07.

Microprocessor Implementations Of Discrete Fourier Transform Machines

Paul Chow, Zvonko G. Vranesic, J. L. Yen, 1979 .

The effect of logic block architecture on FPGA performance

Jonathan Rose, Paul Chow, David Lewis, 1992 .

MIPS-X instruction set and programmer''s manual

Paul Chow, 1986 .

OpenCL memory infrastructure for FPGAs (abstract only)

Paul Chow, S. Alexander Chin, P. Chow, 2012, FPGA '12.

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

Samir Parikh, Lesley Shannon, Paul Chow, 2006, 2006 International Conference on Field Programmable Logic and Applications.

An Enhanced Adaptive Recoding Rotation CORDIC

Paul Chow, Jianfeng Zhang, Hengzhu Liu, 2015, ACM Trans. Reconfigurable Technol. Syst..

The MIPS-X Microprocessor,

Mark Horowitz, Paul Chow, 1985 .

FPGA-based supercomputing: an implementation for molecular dynamics

Paul Chow, Ian Kuon, Aaron Egier, 2004, FPGA '04.

Programming the Nallatech Xeon + multi-FPGA heterogeneous platform

Paul Chow, Manuel Saldana, Arun Patel, 2009, 2009 IEEE Hot Chips 21 Symposium (HCS).

Extracting designs of secure IPs using FPGA CAD tools

Paul Chow, Vincent Mirian, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

A remote memory access infrastructure for global address space programming models in FPGAs

Ruediger Willenberg, Paul Chow, 2013, FPGA '13.

MIPS-X: the external interface

Anant Agarwal, Paul Chow, Arturo Salz, 1987 .

An implementation of a directory protocol for a cache coherent system on FPGAs

Paul Chow, Vincent Mirian, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs

Paul Chow, Manuel Saldaña, P. Chow, 2006, 2006 International Conference on Field Programmable Logic and Applications.

The challenges of using an embedded MPI for hardware-based processing nodes

Paul Chow, Manuel Saldaña, Daniel Le Ly, 2009, 2009 International Conference on Field-Programmable Technology.

CPU-FPGAヘテロジーニアスデータセンターにおける分散ストリーム処理基盤 (コンピュータシステム)

Paul Chow, Naif Tarafdar, 福田エリック駿, 2017 .

Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications

Paul Chow, Yuanxi Peng, Manuel Saldaña, 2014, TRETS.

HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media

Yasmin Afsharnejad, Vaughn Betz, Paul Chow, 2018, HEART.

The External Interface

Paul Chow, 1989 .

Hardware Support for Prescient Instruction Prefetch

John Paul Shen, Hong Wang, Paul Chow, 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

An FPGA Implementation of Reciprocal Sums for SPME

Paul Chow, Sam Lee, P. Chow, 2007, ERSA.

Architectural advances in the VLSI implementation of arithmetic coding for binary image compression

P. Glenn Gulak, Paul Chow, Gennady Feygin, 1994, Proceedings of IEEE Data Compression Conference (DCC'94).

FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack

Paul Chow, J. Gregory Steffan, Hadi Bannazadeh, 2014, FCCM 2014.

A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media

Yasmin Afsharnejad, Vaughn Betz, Paul Chow, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Designing for FPGAs in the Cloud

Thomas Lin, Paul Chow, Naif Tarafdar, 2018, IEEE Design & Test.

Managing mutex variables in a cache-coherent shared-memory system for FPGAs

Paul Chow, Vincent Mirian, 2012, 2012 International Conference on Field-Programmable Technology.

Standardizing the performance assessment of reconfigurable processor architectures

Lesley Shannon, Paul Chow, P. Chow, 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis

Paul Chow, Mustafa Abbas, Andrew Boutros, 2017, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

FPGA Acceleration of MultiFactor CDO Pricing

Paul Chow, Alexander Kaganov, Asif Lakhany, 2011, TRETS.

Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks

Shawki Areibi, Paul Chow, Graham W. Taylor, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Norman P. Jouppi, Paul Chow, Keith I. Farkas, 1996, Proceedings. Second International Symposium on High-Performance Computer Architecture.

Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture

Jiang Jiang, Paul Chow, Zuocheng Xing, 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

A high-performance architecture for training Viola-Jones object detectors

Paul Chow, Charles Lo, 2012, 2012 International Conference on Field-Programmable Technology.

WAM 2.3 A 32b Microprocessor with OnChip ZKbyte Instruction Cache

P. Glenn Gulak, Anant Agarwal, Peter Steenkiste, 1984 .

The multicluster architecture: reducing cycle time through partitioning

Norman P. Jouppi, Paul Chow, Zvonko G. Vranesic, 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

Paul Chow, Manuel Saldaña, Hao Jun Liu, 2012, Int. J. Reconfigurable Comput..

A multiprocessor architecture for Viterbi decoders with linear speedup

P. Glenn Gulak, Paul Chow, Gennady Feygin, 1993, IEEE Trans. Signal Process..

Acceleration of an analytical approach to collateralized debt obligation pricing

Paul Chow, Dharmendra P. Gupta, P. Chow, 2010, FPGA '10.

A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs

Yong Dou, Jie Zhou, Zhiqiang Liu, 2019, Electronics.

Numerical Error Minimizing Floating-Point to Fixed-Point ANSI C Compilation

Paul Chow, P. Chow, 1999 .

OneChip: an FPGA processor with reconfigurable logic

Ralph Wittig, Paul Chow, P. Chow, 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000

Paul Chow, Peter Y. K. Cheung, 2000, FPGA.

Simulation-based HW/SW co-debugging for field-programmable systems-on-chip

Ruediger Willenberg, Paul Chow, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

2011 19th IEEE annual international symposium on field-programmable custom computing machines : (FCCM 2011) : Salt Lake City, Utah, USA 1-3 May 2011

Paul Chow, Mike Wirthlin, P. Chow, 2011 .

Mips-X RISC Microprocessor

Paul Chow, P. Chow, 1989 .

A Field-Programmable Mixed-Analog-Digital Array

P. Glenn Gulak, Paul Chow, P. G. Gulak, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

A CMOS Image Sensor for DNA Microarrays

Samir Parikh, P. Glenn Gulak, Paul Chow, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Leveraging reconfigurability in the design process

Lesley Shannon, Paul Chow, 2005, International Conference on Field Programmable Logic and Applications, 2005..

A VLSI implementation of a cascade Viterbi decoder with traceback

P. Glenn Gulak, Steven J. E. Wilton, Paul Chow, 1993, 1993 IEEE International Symposium on Circuits and Systems.

The routability of multiprocessor network topologies in FPGAs

Lesley Shannon, Paul Chow, Manuel Saldaña, 2006, SLIP '06.

Session details: Integrating FPGAs in high-performance computing

Paul Chow, P. Chow, 2007, Symposium on Field Programmable Gate Arrays.

The effect of logic block complexity on area of programmable gate arrays

Jonathan Rose, Paul Chow, David Lewis, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

An FPGA Processor With Reconfigurable Logic

Paul Chow, Ralph D. Wittig, 1996 .

Minimizing error and VLSI complexity in the multiplication free approximation of arithmetic coding

P. Glenn Gulak, Paul Chow, Gennady Feygin, 1993, [Proceedings] DCC `93: Data Compression Conference.

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008

Paul Chow, Michael D. Hutton, P. Chow, 2008, Symposium on Field Programmable Gate Arrays.

An FPGA-based processor for training convolutional neural networks

Yong Dou, Jingfei Jiang, Paul Chow, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Why Put FPGAs in your CPU socket?

Paul Chow, 2013, FPT.

Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up

Paul Chow, P. G. Gulak, G. Feygin, 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

Galapagos: A Full Stack Approach to FPGA Integration in the Cloud

Varun Sharma, Paul Chow, Naif Tarafdar, 2018, IEEE Micro.

A framework for modeling and optimization of prescient instruction prefetch

John Paul Shen, Hong Wang, Paul Chow, 2003, SIGMETRICS '03.

A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only)

Paul Chow, Ehsan Ghasemi, 2016, FPGA.

Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs

Paul Chow, Vincent Mirian, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor

Paul Chow, Chichyang Chen, 2007, GLSVLSI '07.

The Execute Engine

Paul Chow, 1989 .

A Scalable FPGA-based Multiprocessor

Paul Chow, Manuel Saldaña, Arun Patel, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs

Paul Chow, Vincent Mirian, P. Chow, 2017, IWOCL.

Multi-fidelity Optimization for High-Level Synthesis Directives

Paul Chow, Charles Lo, P. Chow, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

49th Annual Device Research Conference

Hajime Imai, Wolfgang Fichtner, Larry A. Coldren, 1991 .

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method

Jiang Jiang, Yuan Li, Minxuan Zhang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Model-based optimization of High Level Synthesis directives

Paul Chow, Charles Lo, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

Accelerating Apache Spark Big Data Analysis with FPGAs

Paul Chow, Ehsan Ghasemi, P. Chow, 2016, 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress (UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld).

Reduced instruction set computer architectures

Paul Chow, John L. Hennessy, 1988 .

Optimization of field-programmable gate array logic block architecture for speed

Jonathan Rose, Paul Chow, David Lewis, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

Architectural tradeoffs in the design of MIPS-X

Mark Horowitz, Paul Chow, P. Chow, 1987, ISCA '87.

The Transmogrifier-2: a 1 million gate rapid prototyping system

Jonathan Rose, Paul Chow, David M. Lewis, 1997, FPGA '97.

UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs

Paul Chow, Vincent Mirian, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

A high-speed FPGA using programmable mini-tiles

Jonathan Rose, Paul Chow, Soon Ong Seo, 1993 .

The effect of reconfigurable units in superscalar processors

Paul Chow, Jorge E. Carrillo, 2001, FPGA.

DES Cracking on the Transmogrifier 2a

Paul Chow, Ivan Hamer, P. Chow, 1999, CHES.

A high-performance FPGA architecture for restricted boltzmann machines

Paul Chow, Daniel Le Ly, 2009, FPGA '09.

Instruction Fetch Hardware

Paul Chow, 1989 .

Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems

Paul Chow, Andrew W. H. House, 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.

FFIVE: An FPGA Framework for Interactive VNF Environments

Paul Chow, Alberto Leon-Garcia, Mohammad Ewais, 2021, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Pharos: a Multi-FPGA Performance Monitor

Paul Chow, Welson Sun, Arzhang Rafii, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

Exploring PGAS Communication for Heterogeneous Clusters with FPGAs

Paul Chow, Varun Sharma, 2021, FPGA.

Interactive Debugging at IP Block Interfaces in FPGAs

Paul Chow, Marco Antonio Merlini, Isamu Poy, 2021, FPGA.

A Framework Integrating FPGAs in VNF Networks

Paul Chow, Alberto Leon-Garcia, Mohammad Ewais, 2021, 2021 12th International Conference on Network of the Future (NoF).

RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication

Jun Zheng, Paul Chow, Qianfeng Clark Shen, 2021, FPGA.

A PGAS Communication Library for Heterogeneous Clusters pdf

Paul Chow, Varun Sharma, 2021, ArXiv.