T. Izawa

发表

A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders

A. Inoue, R. Ohe, S. Kashiwakura, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

A 500 MHz 288 kb CMOS SRAM macro for on-chip cache

T. Izawa, S. Kawamura, M. Fujita, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

SP 22.4: A 1V 0.9mW at 100MHz 2kx16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25pm Dual-Vt CMOS

T. Izawa, S. Mitarai, Mark Horowitz, 1998 .

A 1 V 0.9 mW at 100 MHz 2 k/spl times/16 b SRAM utilizing a half-swing pulsed-decoder and write-bus architecture in 0.25 /spl mu/m dual-Vt CMOS

T. Izawa, M. Horowitz, S. Mitarai, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).