T. Vandeweyer

发表

In-line metrology for characterization and control of extreme wafer thinning of bonded wafers

E. Beyne, J. De Vos, A. Jourdain, 2017, 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO).

Gate double patterning strategies for 10-nm node FinFET devices

David Hellin, Hubert Hody, Vasile Paraschiv, 2015 .

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

R. Rooyackers, M. Van Hove, K. Ronse, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

A 400GHz fMAX fully self-aligned SiGe:C HBT architecture

S. Decoutere, T. Vandeweyer, S. Van Huylenbroeck, 2009, 2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

R. Rooyackers, E. Augendre, N. Collaert, 2006, 2006 International Electron Devices Meeting.

Spacer defined FinFET: Active area patterning of sub-20nm fins with high density

Rita Rooyackers, Denis Shamiryan, Nadine Collaert, 2007 .

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

G.A.M. Hurkx, S. Decoutere, T. Vanhoucke, 2007, 2007 IEEE International Electron Devices Meeting.

Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application

B. Govoreanu, A. Fantini, N. Jossart, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques

Naoto Horiguchi, Denis Shamiryan, Malgorzata Jurczak, 2011 .

Advanced Cu interconnects using air gaps

J. Michelon, Alexis Farcy, Roel Daamen, 2005 .

New lithographic requirements for the implant levels in scaled devices

Naoto Horiguchi, Christina Baerts, T. Vandeweyer, 2011 .

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).