Pedro Echeverría

Leakage Energy Reduction in Banked Content Addressable Memories

Marisa López-Vallejo, José Luis Ayala, Pedro Echeverría, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Experimental methodology for power characterization of FPGAs

Marisa López-Vallejo, Miguel Angel Sánchez, Pedro Echeverría, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

An FPGA run-time parameterisable Log-Normal Random Number Generator

Wayne Luk, David B. Thomas, Marisa López-Vallejo, 2008, ARC.

Floating-Point Exponentiation Units for Reconfigurable Computing

Florent de Dinechin, Bogdan Pasca, Marisa López-Vallejo, 2013, TRETS.

Designing highly parameterized hardware using xHDL

Marisa López-Vallejo, Miguel Angel Sánchez, Pedro Echeverría, 2008, 2008 Forum on Specification, Verification and Design Languages.

Power Considerations in Banked CAMs: A Leakage Reduction Approach

Marisa López-Vallejo, José Luis Ayala, Pedro Echeverría, 2008, VLSI Design.

Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs

Marisa López-Vallejo, Carlos A. López-Barrio, Pedro Echeverría, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach

Marisa López-Vallejo, Pedro Echeverría, Jose María Pesquero, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs

Marisa López-Vallejo, Pedro Echeverría, 2011, Microprocess. Microsystems.

High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator

Marisa López-Vallejo, Pedro Echeverría, P. Echeverría, 2013, J. Signal Process. Syst..