Sorin Cotofana

发表

Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms

Kees G. W. Goossens, Anca Mariana Molnos, Ashkan Beyranvand Nejad, 2012, Map2MPSoC/SCOPES.

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic

Derek Abbott, Sorin Cotofana, Peter Celinski, 2004, PATMOS.

Vector ISA Extension for Sparse Matrix-Vector Multiplication

Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis, 1999, Euro-Par.

Functional unit sharing between stacked processors in 3D integrated systems

Sorin Cotofana, Demid Borodin, Winston Siauw, 2011, 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

On the design complexity of the issue logic of superscalar machines

Stamatis Vassiliadis, Sorin Cotofana, S. Vassiliadis, 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

Counter based superscalar instruction issuing

Stamatis Vassiliadis, Ben H. H. Juurlink, Sorin Cotofana, 2000, Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future.

Consciousness for modeling intelligence - simulating the evolution by closure to the inverse

Sorin Cotofana, Tudor Niculiu, Cristian Lupu, 2006, ICINCO-ICSO.

A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM

Guanda Wang, Sorin Cotofana, Youguang Zhang, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Static cache partitioning robustness analysis for embedded on-chip multi-processors

Anca Mariana Molnos, Sorin Cotofana, Jos T. J. van Eijndhoven, 2006, CF '06.

High-Level Energy Estimation for ARM-Based SOCs

Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha, 2004, SAMOS.

Generalized matrix method for efficient residue to decimal conversion

Sorin Cotofana, Kazeem Alagbe Gbolagade, S. Cotofana, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Analog-to-digital converter based on single-electron tunneling transistors

Jianfei Jiang, Sorin Cotofana, Chaohong Hu, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

CMOS Implementation of Generalized Threshold Functions

Stamatis Vassiliadis, Sorin Cotofana, Marius Padure, 2003, IWANN.

Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units

David Declercq, Valentin Savin, Tushar Gupta, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Future Directions of (Programmable and Reconfigurable) Embedded Processors

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2004 .

Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding

Sorin Cotofana, Thomas Marconi, S. Cotofana, 2015, ACM Great Lakes Symposium on VLSI.

Session details: Reliability, Resiliency, Robustness II

Sorin Cotofana, 2015, GLSVLSI 2015.

Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints

Kees G. W. Goossens, Anca Mariana Molnos, Ashkan Beyranvand Nejad, 2012, WESE '12.

A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

Sorin Cotofana, Nicoleta Cucu Laurenciu, S. Cotofana, 2013, Microelectron. Reliab..

Composable local memory organisation for streaming applications on embedded MPSoCs

Kees G. W. Goossens, Ben H. H. Juurlink, Anca Mariana Molnos, 2011, CF '11.

Lifetime reliability assessment with aging information from low-level sensors

Sorin Cotofana, Liang Fang, Yao Wang, 2013, GLSVLSI '13.

Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs

Sorin Cotofana, Changlin Chen, 2014, NoCArc '14.

Complementary Arranged Graphene Nanoribbon-based Boolean Gates

Sorin Cotofana, Yande Jiang, Nicoleta Cucu Laurenciu, 2018, 2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Hierarchical interfaces for hardware software systems

Sorin Cotofana, Chouki Aktouf, Tudor Niculiu, 2000, ESM.

Low cost and energy, thermal noise driven, probability modulated random number generator

Sorin Cotofana, Nicoleta Cucu Laurenciu, S. Cotofana, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Periodic symmetric functions, serial addition, and multiplication with neural networks

Stamatis Vassiliadis, Sorin Cotofana, S. Vassiliadis, 1998, IEEE Trans. Neural Networks.

Implementable building blocks for fluctuation based calculation in single electron tunneling technology

Sorin Cotofana, Innocent Agbo, Saleh Safiruddin, 2009, 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO).

Low cost and latency embedded 3D graphics reciprocation

Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A Taxonomy of Field-Programmable Custom Computing Machines

Stamatis Vassiliadis, Sorin Cotofana, Mihai Sima, 2007 .

Digital to analog conversion performed in single electron technology

Stamatis Vassiliadis, Sorin Cotofana, C. Lageweg, 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

Threshold logic parallel counters for 32-bit multipliers

Derek Abbott, Sorin Cotofana, Peter Celinski, 2002, SPIE Micro + Nano Materials, Devices, and Applications.

Sparse Matrix Vector Multiplication Evaluation Using the BBCS Scheme

Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis, 2001 .

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices

Sorin Cotofana, Liang Fang, Yao Wang, 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

A 3D stacked high performance scalable architecture for 3D Fourier Transform

Sorin Cotofana, Marius Enachescu, George Razvan Voicu, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

Jiaoyan Chen, Alexandru Amaricai, Sorin Cotofana, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

GARBAGE COLLECTION FOR THE DELFT JAVA PROCESSOR

Sorin Cotofana, A. Berlea, S. Cotofana, 2003 .

A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance

Yang Guo, Xu He, Sorin Cotofana, 2017, ACM Great Lakes Symposium on VLSI.

δ-Bit serial binary addition with linear threshold networks

Stamatis Vassiliadis, Sorin Cotofana, S. Vassiliadis, 1996, J. VLSI Signal Process..

A novel virtual age reliability model for Time-to-Failure prediction

Yao Wang, Sorin Cotofana, 2010, 2010 IEEE International Integrated Reliability Workshop Final Report.

Single-electron tunneling transistor implementation of periodic symmetric functions

Jianfei Jiang, Sorin Cotofana, Chaohong Hu, 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

Low cost multi-error correction for 3D polyhedral memories

Sorin Cotofana, Thomas Marconi, George Razvan Voicu, 2017, 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

VASILE: A reconfigurable vector architecture for instruction level frequency scaling

Sorin Cotofana, Lucian Petrica, Valeriu Codreanu, 2013, 2013 IEEE Faible Tension Faible Consommation.

Evaluation Methodology for Single Electron Encoded Threshold Logic Gates

Stamatis Vassiliadis, Sorin Cotofana, Casper Lageweg, 2003, VLSI-SOC.

A Hierarchical sparse matrix storage format for vector processors

Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Ultra low power NEMFET based logic

Antonios Bazigos, Adrian M. Ionescu, Sorin Cotofana, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Hierarchical mixed simulation for intelligent interfaces of microsystems

Sorin Cotofana, T. Niculiu, A. Manolescu, 1999, CAS '99 Proceedings. 1999 International Semiconductor Conference (Cat. No.99TH8389).

Alternatives in FPGA-based SAD implementations

Stephan Wong, Sorin Cotofana, Bastiaan Stougie, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2002, Embedded Processor Design Challenges.

Serial binary multiplication with feed-forward neural networks

Stamatis Vassiliadis, Sorin Cotofana, 1999, Neurocomputing.

Hierarchical approach for hardware/software systems

Sorin Cotofana, T. Niculiu, A. Manolescu, 2000, 2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No.00TH8486).

Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach

Derek Abbott, Stamatis Vassiliadis, Said F. Al-Sarawi, 2004, IEEE Computer Society Annual Symposium on VLSI.

Fast and accurate workload-level neural network based IC energy consumption estimation

Sorin Cotofana, Nicoleta Cucu Laurenciu, 2017, 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors

Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, 2008, 2008 Design, Automation and Test in Europe.

An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability

Bo Yang, Sorin Cotofana, Emanuel Popovici, 2016, 2016 27th Irish Signals and Systems Conference (ISSC).

High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders

Sorin Cotofana, George Razvan Voicu, 2017, IEEE Transactions on Emerging Topics in Computing.

Transmission Channel Noise Aware Energy Effective LDPC Decoding

Sorin Cotofana, Emanuel M. Popovici, Christian Spagnol, 2014, VLSI-SoC.

BBCS Based Sparse Matrix-Vector Multiplication: Initial Evaluation

Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis, 2000 .

Towards energy effective LDPC decoding by exploiting channel noise variability

Sorin Cotofana, Emanuel M. Popovici, Christian Spagnol, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Pel reconstruction on FPGA-augmented TriMedia

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Block Based Compression Storage Expected Performance

Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis, 2002 .

The MOLEN ρμ-coded processor

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2001 .

Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors

Anca Mariana Molnos, Sorin Cotofana, Jos T. J. van Eijndhoven, 2007, Trans. High Perform. Embed. Archit. Compil..

2 Counters and Multiplication with Linear Threshold Logic

Stamatis Vassiliadis, Sorin Cotofana, 1996 .

Efficient hardware for antialiasing coverage mask generation

Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha, 2004 .

Binary multiplication based on single electron tunneling

Stamatis Vassiliadis, Sorin Cotofana, Casper Lageweg, 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case

Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos, Sorin Cotofana, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Emerging non-CMOS nanoelectronic devices - What are they?

Sorin Cotofana, Said Hamdioui, Nor Zaidi Haron, 2009, 2009 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

Asynchronous Charge Sharing Power Consistent

Arnaud Tisserand, Jiaoyan Chen, Sorin Cotofana, 2015 .

Critical transistors nexus based circuit-level aging assessment and prediction

Sorin Cotofana, Nicoleta Cucu Laurenciu, 2014, J. Parallel Distributed Comput..

Concurrent engineering for intelligent simulation

Sorin Cotofana, T. Niculiu, 2003 .

Coarse reconfigurable multimedia unit extension

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2001, Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing.

Design and experimental results of a CMOS flip-flop featuring embedded threshold logic

Stamatis Vassiliadis, Sorin Cotofana, Marius Padure, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Is TSV-based 3D integration suitable for inter-die memory repair?

Sorin Cotofana, Said Hamdioui, Mottaqiallah Taouil, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Is the road towards “Zero-Energy” paved with NEMFET-based power management?

Sorin Cotofana, Marius Enachescu, George Razvan Voicu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Hierarchical Intellignet Mixed Simulation

Sorin Cotofana, Tudor Niculiu, 2002, ESM.

A direct measurement scheme of amalgamated aging effects with novel on-chip sensor

Sorin Cotofana, Yao Wang, Nicoleta Cucu Laurenciu, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Towards “zero-energy” using NEMFET-based power management for 3D hybrid stacked ICs

Sorin Cotofana, Marius Enachescu, George Razvan Voicu, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

SAD implementation in FPGA hardware

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2001 .

MPEG macroblock parsing and pel reconstruction on an FPGA-augmented TriMedia processor

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Compact delay modeling of latch-based threshold logic gates

Stamatis Vassiliadis, Sorin Cotofana, C. Dan, 2002, Proceedings. International Semiconductor Conference.

An O(n) Residue Number System to Mixed Radix Conversion technique

Sorin Cotofana, Kazeem Alagbe Gbolagade, S. Cotofana, 2009, 2009 IEEE International Symposium on Circuits and Systems.

An efficient residue-to-binary converter for the new moduli set {2n/2 ± 1, 22n+1,2n + 1}

Sorin Cotofana, Kazeem Alagbe Gbolagade, Hillary Siewobr, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

Design Tradeoffs for an Embedded OpenGL-Compliant Hardware Rasterizer

Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha, 2003 .

Robust sub-powered asynchronous logic

Arnaud Tisserand, Jiaoyan Chen, Sorin Cotofana, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Efficient Method for Designing Modulo {2n ± k} Multipliers

Leonel Sousa, Sorin Cotofana, Héctor Pettenghi, 2014, J. Circuits Syst. Comput..

Can SG-FET Replace FET in Sleep Mode Circuits?

Adrian M. Ionescu, Sorin Cotofana, Marius Enachescu, 2009, NanoNet.

Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs

Sorin Cotofana, Changlin Chen, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set

Ricardo Chaves, Leonel Sousa, Sorin Cotofana, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Block Save Addition with Threshold Gates

Stamatis Vassiliadis, Sorin Cotofana, J. Hoekstra, 1995 .

CONAN - a design exploration framework for reliable nano-electronics architectures

Yusuf Leblebici, Adrian M. Ionescu, Alexandre Schmid, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

An effective New CRT based reverse converter for a novel moduli set {22n+1 − 1, 22n+1, 22n − 1}

Sorin Cotofana, Kazeem Alagbe Gbolagade, Edem Kwedzo Bankas, 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

Atomistic-Level Hysteresis-Aware Graphene Structures Electron Transport Model

Sorin Cotofana, Yande Jiang, N. Cucu Laurenciu, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Area efficient, high speed parallel counter circuits using charge recycling threshold logic

Derek Abbott, Sorin Cotofana, Peter Celinski, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Error Correction Code protected Data Processing Units

Valentin Savin, Tushar Gupta, Sorin Cotofana, 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Bitstream compression techniques for Virtex 4 FPGAs

Sorin Cotofana, Radu Andrei Stefan, S. Cotofana, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Binary multiplication based on single electron tunneling

Stamatis Vassiliadis, Sorin Cotofana, C. Lageweg, 2004 .

GRAAL: A Framework for Low-Power 3D Graphics Accelerators

Stamatis Vassiliadis, Ben H. H. Juurlink, Sorin Cotofana, 2008, IEEE Computer Graphics and Applications.

Single electron encoded logic memory elements

Stamatis Vassiliadis, Sorin Cotofana, C. Lageweg, 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli set

Sorin Cotofana, Kazeem Alagbe Gbolagade, George Razvan Voicu, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

A shared polyhedral cache for 3D wide-I/O multi-core computing platforms

Sorin Cotofana, George Razvan Voicu, Mihai Lefter, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Multi-level probabilistic timing error reliability analysis using a circuit dependent fault map generation

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2015, 2015 Conference on Design of Circuits and Integrated Systems (DCIS).

Achieving fanout capabilities in single electron encoded logic networks

Sorin Cotofana, C. Lageweg, Stamatis Vassiliadis, 2001, 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443).

Adaptive Clock Scheduling for pipelined structures

Sorin Cotofana, Ben Kuiper, 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

Multi-frequency Data Parallel Spin Wave Logic Gates

Said Hamdioui, Sorin Cotofana, Abdulqader Mahmoud, 2020 .

Enabling vertical wormhole switching in 3D NoC-Bus hybrid systems

Sorin Cotofana, Changlin Chen, Marius Enachescu, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

The future of computing : essays in memory of Stamatis Vassiliadis

Kees Goossens, Sorin Cotofana, Said Hamdioui, 2007 .

Throughput optimization via cache partitioning for embedded multiprocessors

Anca Mariana Molnos, Sorin Cotofana, Jos T. J. van Eijndhoven, 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links

Sorin Cotofana, Changlin Chen, Yaowen Fu, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A composable, energy-managed, real-time MPSOC platform

Kees Goossens, Sorin Cotofana, Anca Molnos, 2010, 2010 12th International Conference on Optimization of Electrical and Electronic Equipment.

Signed Digit Addition and Related Operations with Threshold Logic

Stamatis Vassiliadis, Sorin Cotofana, 2000, IEEE Trans. Computers.

Variation tolerant on-chip degradation sensors for dynamic reliability management systems

Sorin Cotofana, Liang Fang, Yao Wang, 2012, Microelectron. Reliab..

High-level intelligence-oriented simulation

Sorin Cotofana, Chouki Aktouf, T. Niculiu, 2002, Proceedings. International Semiconductor Conference.

Serial Binary Addition with Polynominally Bounded Weights

Stamatis Vassiliadis, Sorin Cotofana, S. Vassiliadis, 1996, ICANN.

NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits

Santosh Kumar Vishvakarma, Sorin Cotofana, Ambika Prasad Shah, 2019 .

From Computability to Simulability

Sorin Cotofana, T. Niculiu, A. Manolescu, 2006 .

A low cost method to tolerate soft errors in the NoC router control plane

Sorin Cotofana, Changlin Chen, 2013, 2013 IEEE International SOC Conference.

A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation

Mahmood Fazlali, Somayeh Timarchi, Sorin Cotofana, 2010, 2010 IEEE International Conference on Computer Design.

n-bit Data Parallel Spin Wave Logic Gate

Said Hamdioui, Sorin Cotofana, Christoph Adelmann, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

GRAAL - a development framework for embedded graphics accelerators

Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices

Sorin Cotofana, Liang Fang, Yao Wang, 2014, J. Parallel Distributed Comput..

Timing error analysis of flooded LDPC decoders

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2015, 2015 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS).

Haar-based interconnect coding for energy effective medium/long range data transport

Sorin Cotofana, Nicoleta Cucu Laurenciu, 2017, 2017 30th IEEE International System-on-Chip Conference (SOCC).

On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps

Sorin Cotofana, Yande Jiang, Nicoleta Cucu Laurenciu, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Stamatis Vassiliadis, Sorin Cotofana, Casper Lageweg, 2005, IEEE Transactions on Computers.

A Markovian, variation-aware circuit-level aging model

Sorin Cotofana, Nicoleta Cucu Laurenciu, 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

An 8-Point IDCT computing resource implemented on a TriMedia/CPU64 reconfigurable functional unit

Stamatis Vassiliadis, Sorin Cotofana, Mihai Sima, 2001 .

A versatile threshold logic gate

Sorin Cotofana, A. Stokman, S. Vasilliadis, 1998, 1998 International Semiconductor Conference. CAS'98 Proceedings (Cat. No.98TH8351).

An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set $\{2n+1,2n,2n-1\}$

Sorin Cotofana, Kazeem Alagbe Gbolagade, George Razvan Voicu, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

c ○ 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2003 .

Compositional memory systems for multimedia communicating tasks

Anca Mariana Molnos, Sorin Cotofana, Jos T. J. van Eijndhoven, 2005, Design, Automation and Test in Europe.

A full adder implementation using SET based linear threshold gates

Stamatis Vassiliadis, Sorin Cotofana, C. Lageweg, 2002, 9th International Conference on Electronics, Circuits and Systems.

Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing

Sorin Cotofana, George Razvan Voicu, 2013, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology

Sorin Cotofana, Cor Meenderinck, 2006, SAMOS.

. FURTHERMORE, THEY PRESENT A MICROCODED MACHINE AUGMENTED WITH FIELD -PROGRAMMABLE GATE ARRAYS (FPGAS) AND PROVIDE EXPERIMENTAL EVIDENCE THAT IT CAN SUBSTANTIALLY INCREASE THE PERFORMANCE OF SOME MEDIA BENCHMARKS . MICROCODE PROCESSING: POSITIONING AND DIRECTIONS

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2003 .

Multimedia enhanced general-purpose processors

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2000, 2000 IEEE International Conference on Multimedia and Expo. ICME2000. Proceedings. Latest Advances in the Fast Changing World of Multimedia (Cat. No.00TH8532).

Hierarchical Testability Assisted Intelligent Simulation

Sorin Cotofana, Chouki Aktouf, T. Niculiu, 2004 .

Capacitive threshold logic: a designer perspective

Stamatis Vassiliadis, Sorin Cotofana, M. Bodea, 1999, CAS '99 Proceedings. 1999 International Semiconductor Conference (Cat. No.99TH8389).

4-output Programmable Spin Wave Logic Gate

Said Hamdioui, Sorin Cotofana, Christoph Adelmann, 2020, 2020 IEEE 38th International Conference on Computer Design (ICCD).

Efficient hardware for antialiasing coverage mask generation

Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha, 2004, Proceedings Computer Graphics International, 2004..

Topic 15+20: Multimedia and Embedded Systems

Stamatis Vassiliadis, Mateo Valero, Francky Catthoor, 2001, Euro-Par.

Variable Length Decoder Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2001 .

Memory-Efficient Dataflow Inference for Deep CNNs on FPGA pdf

Sorin Cotofana, Michaela Blott, Lucian Petrica, 2020, 2020 International Conference on Field-Programmable Technology (ICFPT).

A supply voltage-dependent variation aware reliability evaluation model

Bo Yang, Sorin Cotofana, Emanuel M. Popovici, 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

TFET NDR skewed inverter based sensing method

Sorin Cotofana, Adam Makosiej, Andrei Vladimirescu, 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Analysis of delay mismatching of digital circuits caused by common environmental fluctuations

Antonio Rubio, Sorin Cotofana, Antonio Calomarde, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Energy effective 3D stacked hybrid NEMFET-CMOS caches

Sorin Cotofana, Marius Enachescu, George Razvan Voicu, 2014, 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Single Electron Tunneling based computation

Sorin Cotofana, S. Cotofana, 2010, 2010 27th International Conference on Microelectronics Proceedings.

Adaptive fault-tolerant architecture for unreliable device technologies

Antonio Rubio, Sorin Cotofana, Nivard Aymerich, 2011, 2011 11th IEEE International Conference on Nanotechnology.

Analysis of analog to digital converter based on single-electron tunnelling transistors

Jianfei Jiang, Sorin Cotofana, Chaohong Hu, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Color space conversion for MPEG decoding on FPGA-augmented TriMedia processor

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

Fast Computation of Compound Expressions in Two's Complement Notation

Stamatis Vassiliadis, Sorin Cotofana, Edwin Hakkennes, 2007 .

A sum of absolute differences implementation in FPGA hardware

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2002, Proceedings. 28th Euromicro Conference.

Low Weight and Fan-In Neural Networks for Basic Arithmetic Operations

Sorin Cotofana, S. Cotofana, 2007 .

Microcode Processing: Positioning and Directions

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2003, IEEE Micro.

A low-power threshold logic family

Stamatis Vassiliadis, Sorin Cotofana, C. Dan, 2002, 9th International Conference on Electronics, Circuits and Systems.

Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note)

Henk Corporaal, Stamatis Vassiliadis, Sorin Cotofana, 2000, Euro-Par.

Static buffered SET based logic gates

Stamatis Vassiliadis, Sorin Cotofana, C. Lageweg, 2002, Proceedings of the 2nd IEEE Conference on Nanotechnology.

Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors

Anca Mariana Molnos, Sorin Cotofana, Jos T. J. van Eijndhoven, 2009, J. Signal Process. Syst..

Stigmergic search with Single Electron Tunneling technology based Memory Enhanced Hubs

Ferdinand Peper, Sorin Cotofana, Saleh Safiruddin, 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Compositional memory systems for data intensive applications

Anca Mariana Molnos, Sorin Cotofana, Jos T. J. van Eijndhoven, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

High radix addition via conditional charge transport in single electron tunneling technology

Sorin Cotofana, Casper Lageweg, Cor Meenderinck, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

LDPC-Based Adaptive Multi-Error Correction for 3D Memories

Valentin Savin, Sorin Cotofana, Thomas Marconi, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs

Sorin Cotofana, Changlin Chen, 2013, 2013 Euromicro Conference on Digital System Design.

A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n}

Sorin Cotofana, Kazeem Alagbe Gbolagade, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits

Sorin Cotofana, Demid Borodin, Saleh Safiruddin, 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits

Sorin Cotofana, Liang Fang, Yao Wang, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

Electron counting based high-radix multiplication in single electron tunneling technology

Sorin Cotofana, Cor Meenderinck, C. Meenderinck, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Microcoded Reconfigurable Embedded Processors: Current Developments

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2002, Embedded Processor Design Challenges.

Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits

Ferdinand Peper, Sorin Cotofana, Saleh Safiruddin, 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip

Sorin Cotofana, Changlin Chen, Ye Lu, 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

Brownian Circuits: Designs

Yasuo Takahashi, Tetsuya Shimokawa, Ferdinand Peper, 2016, Int. J. Unconv. Comput..

Field-Programmable Custom Computing Machines - A Taxonomy -

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2002, FPL.

D-SAB: A Sparse Matrix Benchmark Suite

Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis, 2003, PaCT.

Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA

Sorin Cotofana, Michaela Blott, Lucian Petrica, 2020, GECCO.

General-purpose processor Huffman encoding extension

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2000, Proceedings International Conference on Information Technology: Coding and Computing (Cat. No.PR00540).

Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits

Jiaoyan Chen, Sorin Cotofana, Emanuel M. Popovici, 2015, Microelectron. Reliab..

On computing addition related arithmetic operations via controlled transport of charge

Stamatis Vassiliadis, Sorin Cotofana, Casper Lageweg, 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

Asynchronous Charge Sharing Power Consistent Montgomery Multiplier

Arnaud Tisserand, Jiaoyan Chen, Sorin Cotofana, 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.

Color Space Conversion on FPGA-augmented TriMedia-32 Processor

Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, 2002 .

Spin Wave Normalization Toward All Magnonic Circuits

Abdulqader Mahmoud, Sorin Cotofana, Said Hamdioui, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Hybrid adaptive clock management for FPGA processor acceleration

Sorin Cotofana, Lucian Petrica, Alexandru Gheolbanoiu, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

The MOLEN rho-mu-Coded Processor

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2001, FPL.

Compositional, efficient caches for a chip multi-processor

Anca Mariana Molnos, Sorin Cotofana, Jos T. J. van Eijndhoven, 2006, Proceedings of the Design Automation & Test in Europe Conference.

ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits

Sorin Cotofana, Emanuel M. Popovici, Satish Grandhi, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

3D stacked wide-operand adders: A case study

Sorin Cotofana, Marius Enachescu, George Razvan Voicu, 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

An Energy-Aware Architectural Exploration Tool for ARM-Based SOCs

Sorin Cotofana, D. Crisu, 2001 .

A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement

Georgios Ch. Sirakoulis, Sorin Cotofana, Antonio Rubio, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

2-1 Additions and Related Arithmetic Operations with Threshold Logic

Stamatis Vassiliadis, Sorin Cotofana, Koen Bertels, 1996, IEEE Trans. Computers.

2-Output Spin Wave Programmable Logic Gate

Said Hamdioui, Sorin Cotofana, Christoph Adelmann, 2020, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Context aware slope based transistor-level aging model

Sorin Cotofana, Nicoleta Cucu Laurenciu, 2012, Microelectron. Reliab..

Graphene-Based Artificial Synapses with Tunable Plasticity

Sorin Cotofana, Yande Jiang, Nicoleta Cucu Laurenciu, 2021, ACM J. Emerg. Technol. Comput. Syst..

Multifrequency Data Parallel Spin Wave Logic Gates

Sorin Cotofana, Said Hamdioui, Christoph Adelmann, 2021, IEEE Transactions on Magnetics.

Spin Wave Based Full Adder

Sorin Cotofana, Said Hamdioui, Christoph Adelmann, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Spin Wave Based 4-2 Compressor

Sorin Cotofana, Said Hamdioui, Christoph Adelmann, 2021, 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS).

Spin Wave Normalization Toward All Magnonic Circuits

Abdulqader Mahmoud, Sorin Cotofana, Said Hamdioui, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Fan-out of 2 Triangle Shape Spin Wave Logic Gates

Sorin Cotofana, Said Hamdioui, Christoph Adelmann, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Achieving Wave Pipelining in Spin Wave Technology

Sorin Cotofana, Said Hamdioui, Christoph Adelmann, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

FSM non-minimal state encoding for low power

Sorin Cotofana, Ben Juurlink, M. Koegst, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

HIERARCHICAL INTELLIGENT SIMULATION

Sorin Cotofana, Tudor Niculiu, 2003 .

On Teaching Embedded Systems Design to Electrical Engineering Students

Stephan Wong, Sorin Cotofana, 2002 .

A linear threshold gate implementation in single electron technology

Stamatis Vassiliadis, Sorin Cotofana, C. Lageweg, 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

Santanu Mahapatra, Sorin Cotofana, Adam Makosiej, 2016 .

Embedded Processors: Characteristics and Trends

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, 2004 .

Energy-Managed , Real-Time MPSOC Platform

Sorin Cotofana, Jude Angelo Ambrose, Radu Stefan, 2010 .

Energy-Efficient Computation of L1 and L2 Norms on a FPGA SIMD Accelerator, with Applications to Visual Search

Sorin Cotofana, Radu Hobincu, Lucian Petrica, 2014 .

High-speed hybrid threshold-Boolean logic counters and compressors

Stamatis Vassiliadis, Sorin Cotofana, M. Padure, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

Direct and Transposed Sparse Matrix-Vector Multiplication

Sorin Cotofana, 2002 .