Noriyuki Homma

发表

Youji Idei, H. Nambu, Kazuo Kanetani, 1991, 1991 Symposium on VLSI Circuits.

A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram

Keiichi Higeta, M. Usami, Masayuki Ohayashi, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

4–kbit bipolar RAM with on–chip address latch function

Kunihiko Yamaguchi, H. Nambu, Kazuo Kanetani, 1987 .

High-speed SRAM Circuit Technology「A 1.8ns Access, 550MHz 4.5Mb CMOS SRAM」「Synonym Hit RAM: A 500MHz 1.5ns CMOS SRAM Macro with 576b Parallel Comparison and Parity Check Functions」

Keiichi Higeta, M. Usami, Y. Fujimura, 1998 .

High-speed Sensing Techniques for

Kunihiko Yamaguchi, Youji Idei, Kenichi Ohhata, 1992 .

An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM

Kenichi Ohhata, Kazuo Kanetani, Noriyuki Homma, 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

Redundancy Technique for Ultra-High-Speed Static RAMs

Kunihiko Yamaguchi, Youji Idei, Kenichi Ohhata, 1993 .

Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOS SRAM

Masayuki Ohayashi, Youji Idei, H. Nambu, 1996 .

A BiCMOS Circuit Using a Base-Boost Technique for Low-Voltage, Low-Power Application

H. Nambu, Kenichi Ohhata, Kazuo Kanetani, 1996 .

Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time

Youji Idei, H. Nambu, Kazuo Kanetani, 1992, Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.

IEEE 1988 Bipolar Circuits E Tdnology Meeting 'An Experimental Soft-error Immune 64-Kb 3ns ECL Bipolar RAM"

Kunihiko Yamaguchi, Noriyuki Homma, Katsumi Ogiue, 1988 .

Diode decoder circuits for ultrahigh‐speed memory

Kunihiko Yamaguchi, H. Nambu, Noriyuki Homma, 1993 .

Storage device with fast word line load circuits

Noriyuki Homma, Kunihiko Yamagushi, 1980 .

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM

Keiichi Higeta, M. Usami, M. Nishiyama, 2000 .

A novel BiCMOS circuit using a base boost technique for low voltage application

H. Nambu, Kazuo Kanetani, Noriyuki Homma, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

Kunihiko Yamaguchi, Kazuo Kanetani, Noriyuki Homma, 1986 .

Clock Distributing System Using Transmission Lines with Guards

Noriyuki Homma, Eiichi Goto, 1995 .

Characteristics of high‐speed bipolar RAMs under address‐skew condition

Kunihiko Yamaguchi, Noriyuki Homma, 1992 .

4829361 Semiconductor device

Kazuo Nakazato, Noriyuki Homma, Kazuhiko Sagara, 1990 .

A redundancy technique for ultra-high-speed SRAMs

Youji Idei, H. Nambu, Kazuo Kanetani, 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

Keiichi Higeta, M. Usami, Masayuki Ohayashi, 1995 .

Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro

Keiichi Higeta, Kunihiko Yamaguchi, H. Nambu, 1998 .

Study on discharge circuits for word‐lines in high‐speed bipolar rams

Kunihiko Yamaguchi, Noriyuki Homma, Yoshiaki Sakurai, 1991 .

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

Kunihiko Yamaguchi, Youji Idei, H. Nambu, 1992 .

Process and device technologies for high speed self-aligned bipolar transistors

Noriyuki Homma, Katsuyoshi Washio, Takahiro Onai, 1995 .

Noise Reduction Techniques for a 64kb ECL-CMOS SRAM with a 2ns Cycle Time (Special Issue on LSI Memories)

Youji Idei, Kenichi Ohhata, H. Nambu, 1993 .

A 1.5-ns access time, 78-μm2 memory-cell size, 64-kb ECL-CMOS SRAM

Youji Idei, H. Nambu, Kazuo Kanetani, 1992 .

Time, 78-pm' Memory-Cell Size, 64-kb ECL-CMOS SRAM

Kunihiko Yamaguchi, Youji Idei, Kenichi Ohhata, 1992 .

A 3.5ns, 2W, 20mm216Kb ECL bipolar RAM

H. Nambu, Kazuo Kanetani, Noriyuki Homma, 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

High-speed sensing techniques for ultrahigh-speed SRAMs

Kunihiko Yamaguchi, Youji Idei, H. Nambu, 1992 .

SEPIA: a new isolation structure for soft-error-immune LSIs

Noriyuki Homma, Takahiro Onai, Tohru Nakamura, 1993 .

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

Kunihiko Yamaguchi, Kazuo Kanetani, Noriyuki Homma, 1989 .

Soft-error immune switched-load-resistor memory cell

Kazuo Nakazato, Noriyuki Homma, Takahiro Onai, 1987, 1987 Symposium on VLSI Technology.

Ultra-small high-speed bipolar transistor with sidewall silicide technology

Yoichi Tamaki, Noriyuki Homma, Takahiro Onai, 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.