K. Ohhata

A 1.5ns, 64kb ECL-CMOS SRAM

Youji Idei, H. Nambu, Kazuo Kanetani, 1991, 1991 Symposium on VLSI Circuits.

Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time

Youji Idei, H. Nambu, Kazuo Kanetani, 1992, Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.

A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems

K. Ohhata, N. Shiramizu, M. Sonehara, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A novel BiCMOS circuit using a base boost technique for low voltage application

H. Nambu, Kazuo Kanetani, Noriyuki Homma, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

High‐speed self‐aligned SiGe HBT and application to optical‐fiber‐link ICs

K. Ohhata, Masao Kondo, Katsuyoshi Washio, 2002 .

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

Kunihiko Yamaguchi, Youji Idei, H. Nambu, 1992 .

43 Gb/s full-rate-clock 16:1 multiplexer and 1:16 demultiplexer with SFI-5 interface in SiGe BiCMOS technology

K. Ohhata, N. Shiramizu, S. Yabuki, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

High-speed sensing techniques for ultrahigh-speed SRAMs

Kunihiko Yamaguchi, Youji Idei, H. Nambu, 1992 .