T. Schram

发表

Time-dependent variation: A new defect-based prediction methodology

A. Asenov, G. Groeseneken, B. Kaczer, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Low-frequency noise of advanced memory devices

E. Simoen, C. Claeys, R. Ritzenthaler, 2015, 2015 International Conference on Noise and Fluctuations (ICNF).

2D materials: roadmap to CMOS integration

C. Huyghebaert, A. Leonhardt, D. Lin, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Key issues and techniques for characterizing time-dependent device-to-device variation of SRAM

A. Asenov, G. Groeseneken, B. Kaczer, 2013, 2013 IEEE International Electron Devices Meeting.

A test-proven As-grown-Generation (A-G) model for predicting NBTI under use-bias

S. De Gendt, G. Groeseneken, B. Kaczer, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

B. Parvais, A. Brand, N. Horiguchi, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

D. Mocuta, R. Ritzenthaler, N. Horiguchi, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology

B. Parvais, E. Simoen, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

B. Parvais, S. Van Elshocht, A. Brand, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 Symposium on VLSI Technology.

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

A. Akheyar, T. Chiarella, C. Vrancken, 2008, 2008 Symposium on VLSI Technology.

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

L. Witters, H. Bender, T. Chiarella, 2010, 2010 Symposium on VLSI Technology.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Interface passivation mechanisms in metal gated oxide capacitors

S. De Gendt, M. Heyns, T. Schram, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Processing impact on the reliability of single metal dual dielectric (SMDD) gate stacks

R. Degraeve, G. Groeseneken, S. Biesemans, 2009, 2009 IEEE International Reliability Physics Symposium.

Estimation of fixed charge densities in hafnium-silicate gate dielectrics

S. De Gendt, S. Van Elshocht, L. Pantisano, 2006, IEEE Transactions on Electron Devices.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

B. Parvais, S. Biesemans, T. Schram, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Scaling of high-k dielectrics towards sub-1nm EOT

S. De Gendt, D. Pique, S. Van Elshocht, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

S. De Gendt, S. Van Elshocht, A. Akheyar, 2007, 2007 IEEE International Electron Devices Meeting.

On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

L. Pantisano, G. Groeseneken, A. Kerber, 2003, IEEE Electron Device Letters.

Zero-thickness multi work function solutions for N7 bulk FinFETs

N. Horiguchi, T. Schram, P. Matagne, 2016, 2016 IEEE Symposium on VLSI Technology.

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

N. Collaert, J. Mitard, M. Jurczak, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology

C. Ortolland, A. Akheyar, T. Chiarella, 2006, 2009 Symposium on VLSI Technology.

Ion-implantation-based low-cost Hk/MG process for CMOS low-power application

R. Degraeve, C. Ortolland, W. Vandervorst, 2010, 2010 Symposium on VLSI Technology.

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

E. Simoen, R. Ritzenthaler, N. Horiguchi, 2014, 2014 IEEE International Electron Devices Meeting.

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs

S. De Gendt, L. Pantisano, A. Kerber, 2003, IEEE International Electron Devices Meeting 2003.

The Impact of Stacked Cap Layers on Effective Work Function With HfSiON and SiON Gate Dielectrics

S. Van Elshocht, A. Akheyar, S. Biesemans, 2008, IEEE Electron Device Letters.

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

E. Simoen, E. Vecchio, H. Bender, 2013, 2013 Symposium on VLSI Technology.

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

E. Augendre, A. Veloso, S. Biesemans, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

H. Bender, G. Eneman, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Positive and negative bias temperature instability in La2O3 and Al2O3 capped high-k MOSFETs

R. Degraeve, B. Kaczer, A. Akheyar, 2009, 2009 IEEE International Reliability Physics Symposium.

High performing 8 A EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown (SPER) junctions

S. De Gendt, S. Severi, G. Groeseneken, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

S. De Gendt, N. Collaert, W. Boullart, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..