Toshihiko Mori

发表

A new definition of complexity factor of cold forging process

Toshihiko Mori, Suyang Li, 2009 .

Considerations in Establishment of Artificial Neural Network for Forging Process Design

Toshihiko Mori, Suyang Li, 2006 .

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE

Eiji Yoshida, Hiroshi Yamazaki, Toshihiko Mori, 2014, IEEE Journal of Solid-State Circuits.

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

Kouichi Kanda, Takao Sasaki, Toshihiko Mori, 2012, 2012 IEEE International Solid-State Circuits Conference.

Non-binary SAR ADC with digital error correction for low power applications

Nobukazu Takai, Toshihiko Mori, Haruo Kobayashi, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

Yoshiyasu Doi, Takayuki Shibasaki, Win Chaivipas, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Challenges and Possible Solutions in Enhancing Operational Risk Measurement

Toshihiko Mori, Junji Hiwatashi, Koukichi Ide, 2000 .

SAR ADC Architecture with Digital Error Correction

Nobukazu Takai, Toshihiko Mori, Haruo Kobayashi, 2010 .

Automatic Customization Rule Generation for Electronic Sales Promotion in Wholesale Industry

Toshihiko Mori, Norihisa Komoda, Masaki Yumoto, 1999 .

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing

Sanroku Tsukamoto, Toshihiko Mori, Masato Yoshioka, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Internal Risk Based Approach -- Evolutionary Approaches to Regulatory Capital Charge for Operational Risk --

Toshihiko Mori, Eiji Harada, 2000 .

Copying apparatus with a selectable copying magnification

Shinichi Nakamura, Toshihiko Mori, Masayuki Hirose, 1985 .

422 Proposal of Micro Piercing Process Utilizing Flying Object for Punch

Shinkoh Senda, Toshihiko Mori, Kenji Hirota, 2001 .

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI

Yoichi Koyanagi, Takuji Yamamoto, Hirotaka Tamura, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

SAR ADC Algorithm with Redundancy and Digital Error Correction

Nobukazu Takai, Toshihiko Mori, Haruo Kobayashi, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A fer Amplifier an Encoded Bus Amhikc ower S

Toshihiko Mori, Shigetoshi Wakayama, Makoto Hamaminato, 1997 .

Process Design by Fusion of Process Simulation and Artificial Intelligent

Toshihiko Mori, Suyang Li, 2004 .

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications

Toshihiko Mori, Hiroyuki Nakamoto, Masahiro Kudo, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A Charge-Transfer-Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's

Toshihiko Mori, Shigetoshi Wakayama, Makoto Hamaminato, 1997 .

Maintaining Variety of Solutions by an Adjustment System for Foraging Criteria in BCO

Yasuhiro Suzuki, Toshihiko Mori, Maki Furukawa, 2016 .

Thread Forming by PCR.

Toshihiko Mori, Kunihiko Nakashima, 1997 .

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS

Takayuki Shibasaki, Yoichi Koyanagi, Hirotaka Tamura, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

430 Application of GA Technology to Process Planning for Bending Operation

Toshihiko Mori, Kenji Hirota, Mai Miyawaki, 2001 .

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS

Takayuki Shibasaki, Yoichi Koyanagi, Hirotaka Tamura, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Customization rule generation for electronic sales promotion system in wholesale industry

Toshihiko Mori, Norihisa Komoda, Masaki Yumoto, 1999, Proceedings of International Workshop on Advance Issues of E-Commerce and Web-Based Information Systems. (Cat. No.PR00334).

Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design

Naoki Hamada, Teruo Ishihara, Yukito Tsunoda, 2019, GECCO.

The Honey Bee Optimization by Mimicking a Threshold Regulating in Honey Bee Foraging

Yasuhiro Suzuki, Toshihiko Mori, Maki Furukawa, 2012 .

Dynamic Optimization of Logistics System by Multi-agent system

Toshihiko Mori, Mitsuru Oyaba, 2004 .

Low-Crosstalk Simultaneous 16-Channel × 25 Gb/s Operation of High-Density Silicon Photonics Optical Transceiver

Toshihiko Mori, Tomoyuki Akiyama, Seok-Hwan Jeong, 2017, Journal of Lightwave Technology.

Ultralow-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach–Zehnder Modulator and 28-nm CMOS Driver

Toshihiko Mori, Seok-Hwan Jeong, Shinsuke Tanaka, 2018, Journal of Lightwave Technology.