N. A. Avdeev

Verification of VHDL Descriptions Networks of Synchronous Finite State Machines

P. N. Bibilo, A. E. Kolodenkova, N. A. Avdeev, 2018 .

Logical optimization efficiency in the synthesis of combinational circuits

P. N. Bibilo, N. A. Avdeev, 2015 .

Determination of the delay of a programmable logic array

P. N. Bibilo, N. A. Avdeev, N. Avdeev, 2010 .

A System for Logical Design of Custom CMOS VLSI Functional Blocks with Reduced Power Consumption

P. N. Bibilo, V. I. Romanov, N. A. Avdeev, 2018, Russian Microelectronics.

Verification and Scheme Implementation of Parallel Automata

V. I. Romanov, N. A. Avdeev, P. N. Bibilo, 2020 .

Design of Digital Operational Units with Low Power Consumption

N. A. Avdeev, P. N. Bibilo, 2021 .