Jithendra Srinivas

Clock gating for power optimization in ASIC design cycle theory & practice

Jagdish C. Rao, H. Udayakumar, Sukumar Jairam, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Locality-aware mapping and scheduling for multicores

Mahmut T. Kandemir, Yuanrui Zhang, Wei Ding, 2013, Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO).

Clock gating approaches by IOEX graphs and cluster efficiency plots

Sukumar Jairam, Jithendra Srinivas, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Compiler Directed Data Locality Optimization for Multicore Architectures

Mahmut T. Kandemir, Mustafa Karaköy, Wei Ding, 2011, 2011 International Conference on Parallel Architectures and Compilation Techniques.

Reactive tiling

Mahmut T. Kandemir, Wei Ding, Jithendra Srinivas, 2015, 2015 IEEE/ACM International Symposium on Code Generation and Optimization (CGO).

Clock gating effectiveness metrics: Applications to power optimization

S. Jairam, H. Udayakumar, Jithendra Srinivas, 2009, 2009 10th International Symposium on Quality Electronic Design.

Recognition of machine cells in a group technology layout using self-organizing neural networks

M Ananda Rao, Jithendra Srinivas, M Sreenivasa Rao, 2001 .