Michelly de Souza

发表

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2008 .

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

Denis Flandre, Bruna Cardoso Paz, Marcelo Antonio Pavanello, 2013, Microelectron. Reliab..

A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2013 .

Study of Matching Properties of Graded-Channel SOI MOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2008 .

An explicit multi-exponential model for semiconductor junctions with series and shunt resistances

Juan Muci, Marcelo Antonio Pavanello, Francisco J. García-Sánchez, 2011, Microelectron. Reliab..

Submicrometer graded-channel SOI MOSFET modeling for low temperature analog circuit design

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2006 .

Impact of temperature reduction and channel engineering on the linearity of FD SOI nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Cor Claeys, 2009 .

Comparison of Asymmetric Self-Cascode and Graded-Channel Structures for High Performance Analog SOI MOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2012 .

Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2016, IET Circuits Devices Syst..

A new method for junctionless transistors parameters extraction

Renan Trevisoli Doria, Sylvain Barraud, Marcelo Antonio Pavanello, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Performance of Common-Source, Cascode and Wilson Current Mirrors Implemented with Graded Channel SOI nMOSFETs in a Wide Temperature Range

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2009 .

Low Temperature and Channel Engineering Influence on the Behavior of Analog Source-Follower Buffers

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2008 .

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Maud Vinet, Sylvain Barraud, Olivier Faynot, 2021, ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).

The zero temperature coefficient in junctionless nanowire transistors

Marcelo Antonio Pavanello, Isabelle Ferain, Michelly de Souza, 2012 .

Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short Wavelengths

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2011 .

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its Dependence on the Temperature

Michelly de Souza, Marcelo A. Pavanello, Rodrigo T. Doria, 2012 .

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2015 .

Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion

Abhinav Kranti, Jean-Pierre Colinge, Marcelo Antonio Pavanello, 2011 .

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Maud Vinet, Sylvain Barraud, Olivier Faynot, 2017 .

Trap density characterization through low-frequency noise in junctionless transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2013 .

A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2005 .

Threshold voltage in junctionless nanowire transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2011 .

Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2014 .