T. Efland

Optimized 25 V, 0.34 m/spl Omega//spl middot/cm/sup 2/ very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS process

H.-T. Yuan, Chin-Yu Tsai, J. Arch, 1996, International Electron Devices Meeting. Technical Digest.

7 to 30V state-of-art power device implementation in 0.25 /spl mu/m LBC7 BiCMOS-DMOS process technology

T. Efland, S. Pendharkar, B. Todd, 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

Peripheral motor drive PIC concerns for integrated LDMOS technologies

T. Efland, B. Smith, S. Pendharkar, 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

Wafer chip scale packages with efficient power dissipation have small foot-print for portable applications

T. Efland, Quang Mai, S. Koduri, 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

Performance trade-offs and optimization of low side low voltage integrated FETs

T. Efland, S. Pendharkar, R. Ramanathan, 2004, Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting.

High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process

H. Shichijo, D. Mosher, T. Efland, 2000, 30th European Solid-State Device Research Conference.

Class D digital power amp (PurePath Digital/spl trade/) high Q musical content

L. Risbo, T. Efland, F. Nyboe, 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

A Rugged LDMOS for LBC5 Technology

T. Efland, S. Pendharkar, P. Hower, 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

A 0.7 /spl mu/m linear BiCMOS/DMOS technology for mixed-signal/power applications

T. Efland, J. Erdeljac, L. Hutter, 1997, Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting.