J. Allan

A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM

Rajiv V. Joshi, Stanley E. Schuster, Barbara A. Chappell, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

Rajiv V. Joshi, Stanley E. Schuster, R. L. Franch, 1991 .

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

J.Y.-C. Sun, Stanley E. Schuster, Phillip J. Restle, 1989 .