S. Watanabe

发表

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)

Yukihito Oowaki, Kazunori Ohuchi, Daisaburo Takashima, 1997 .

Folded-read And Open/folded-restore Bit-line Scheme For Giga Scale 6f2 Dram Cell

Shigeyoshi Watanabe, Tohru Ozaki, Yukihito Oowaki, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

Word-line Architecture For Constant Reliability 64Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1991, 1991 Symposium on VLSI Circuits.

New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell

Yukihito Oowaki, Keiji Mabuchi, Shigeyoshi Watanabe, 1995 .

A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs (Special Issue on Low-Power LSI Technologies)

Tohru Ozaki, Yukihito Oowaki, Shigeyoshi Watanabe, 1996 .

A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization

F. Masuoka, K. Sakui, S. Aritome, 1989 .

Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications

J. Matsunaga, H. Nii, T. Yamada, 2002 .

A physically based base pushout model for submicrometer BJTs in the presence of velocity overshoot

Shigeyoshi Watanabe, Kazuya Matsuzawa, Tsuneaki Fuse, 1992 .

Threshold decision method for subtractive color process for lossless compression

Y. Miura, Shigeyoshi Watanabe, Ayumu Akaoka, 2011, Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

Word-line architecture for highly reliable 64-Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1992 .

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1995 .

Handwriting Multi-Tablet Application Supporting Ad Hoc Collaborative Work

Shigeyoshi Watanabe, Makoto Oya, Taisuke Inoue, 2015 .

The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer

Shigeyoshi Watanabe, M. M. Hafizur Rahman, Yasuyuki Miura, 2017, IEICE Trans. Inf. Syst..

Design method of stacked type thermally assisted MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .

Analysis of bit cost and performance for stacked type chain PRAM

Sho Kato, Shigeyoshi Watanabe, Sho Kato, 2013 .

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

Yukihito Oowaki, Shigeyoshi Watanabe, Akihiro Nitayama, 1987 .

Design technology of stacked NAND-type FeRAM with two-transistor-type memory cell

Shigeyoshi Watanabe, Koichi Sugano, S. Watanabe, 2013 .

Design methodology for system LSI with TIS (trench‐isolated transistor using sidewall gate)

Shigeyoshi Watanabe, S. Watanabe, 2006 .

Design Scheme Considering Memory Cell Array Noise for Stacked Type MRAM with NAND Structured Cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .

Novel cell array noise cancelling design scheme for stacked type MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .

Resistive superconducting transition of vanadium films

K. Okamoto, S. Watanabe, M. Awano, 1979 .

10-2 Stand-by/Active Mode Logic for Sub-I V 1G/4Gb DRAMs

Shigeyoshi Watanabe, Kazunori Ohuchi, Daisaburo Takashima, 1992 .