E. Litta

发表

ALD Mo for Advanced MOL Local Interconnects

N. Horiguchi, N. Jourdan, J. Maes, 2022, 2022 IEEE International Interconnect Technology Conference (IITC).

Interface engineering of Ge using thulium oxide

V. Dhanak, M. Östling, I. Mitrovic, 2013 .

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery

R. Ritzenthaler, A. Chasin, N. Horiguchi, 2022, 2022 IEEE International Reliability Physics Symposium (IRPS).

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, 2018 IEEE Symposium on VLSI Technology.

Atomic-layer deposited thulium oxide as a passivation layer on germanium

V. Dhanak, M. Östling, I. Mitrovic, 2015 .

High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O

Mikael Östling, Eugenio Dentoni Litta, Per-Erik Hellström, 2013 .

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Naoto Horiguchi, Tom Schram, Farid Sebaai, 2018 .

Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology

E. D. Litta, E. Litta, 2014 .

Characterization of high-k dielectrics using MeV elastic scattering of He ions

D. Primetzhofer, C. Zoller, E. Litta, 2015 .

Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices

N. Horiguchi, L. Ragnarsson, J. Mitard, 2021, International Electron Devices Meeting.

Novel forksheet device architecture as ultimate logic scaling device towards 2nm

J. Ryckaert, D. Verkest, P. Weckx, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2021, 2021 Symposium on VLSI Technology.

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation

Naoto Horiguchi, Dimitri Linten, Jacopo Franco, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Ultra-thin film and interface analysis of high-k dielectric materials employing Time-Of-Flight Medium Energy Ion Scattering (TOF-MEIS)

G. Possnert, D. Primetzhofer, M. Linnarsson, 2013, 1309.0611.

Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper

A. Vandooren, Naoto Horiguchi, Dimitri Linten, 2021, 2021 International Conference on IC Design and Technology (ICICDT).

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Improving the low-frequency noise performance of input/output DRAM peripheral pMOSFETs

R. Ritzenthaler, T. Schram, N. Horiguchi, 2017, 2017 International Conference on Noise and Fluctuations (ICNF).

Low-frequency noise in high-k LaLuO3/TiN MOSFETs

B. Malm, M. Ostling, E. D. Litta, 2012, 2011 International Semiconductor Device Research Symposium (ISDRS).

Low-frequency noise in high-k LaLuO 3 /TiN MOSFETs

B. Malm, M. Östling, P. Hellström, 2011 .

Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability

R. Ritzenthaler, N. Horiguchi, D. Linten, 2020, IEEE Transactions on Device and Materials Reliability.

Improved low-frequency noise for 0.3nm EOT thulium silicate interfacial layer

Mikael Östling, Eugenio Dentoni Litta, B. Gunnar Malm, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

A study of low-frequency noise on high-k/metal gate stacks with in situ SiOx interfacial layer

B. Malm, M. Ostling, P. Hellstrom, 2013, 2013 22nd International Conference on Noise and Fluctuations (ICNF).

Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors.

A. D. Smith, M. Ostling, A. Smith, 2015, Nanoscale.

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

H. Mertens, R. Ritzenthaler, Z. Tao, 2020, 2020 IEEE Symposium on VLSI Technology.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, IEEE Transactions on Electron Devices.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 Symposium on VLSI Technology.

Buried Power Rail Metal exploration towards the 1 nm Node

H. Mertens, K. Devriendt, J. Geypen, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Middle-of-line plasma dry etch challenges for buried power rail integration

H. Mertens, N. Horiguchi, A. Veloso, 2022, Advanced Lithography.

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Christopher J. Wilson, B. T. Chan, H. Mertens, 2020, IEEE Transactions on Electron Devices.

Buried power SRAM DTCO and system-level benchmarking in N3

J. Ryckaert, P. Weckx, A. Spessot, 2020, 2020 IEEE Symposium on VLSI Technology.

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

J. Ryckaert, T. Chiarella, N. Horiguchi, 2020, 2020 IEEE Symposium on VLSI Technology.

Buried power rail integration for CMOS scaling beyond the 3 nm node

H. Mertens, Z. Tao, G. Mannaert, 2022, Advanced Lithography.

Barrierless ALD Molybdenum for Buried Power Rail and Via-to-Buried Power Rail metallization

N. Horiguchi, N. Jourdan, N. Heylen, 2022, International Interconnect Technology Conference.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

H. Mertens, Z. Tao, K. Devriendt, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Insights into Scaled Logic Devices Connected from Both Wafer Sides

A. Jourdain, E. Beyne, A. De Keersgieter, 2022, International Electron Devices Meeting.

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2022, 2022 International Electron Devices Meeting (IEDM).

Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology

Hao Yu, Julien Ryckaert, Alessio Spessot, 2020, IEEE Transactions on Electron Devices.

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Naoto Horiguchi, Alessio Spessot, Eugenio Dentoni Litta, 2021 .

Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

D. Tsvetanova, N. Horiguchi, J. Ryckaert, 2022, International Electron Devices Meeting.

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections

A. Jourdain, A. Hikavyy, G. Mannaert, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Two-level MOL and VHV routing style to enable extreme height scaling beyond 2nm technology node

D. Jang, A. Spessot, J. Ryckaert, 2021, 2021 IEEE International Interconnect Technology Conference (IITC).

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

M. Östling, P. Hellström, E. Litta, 2015 .

Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond

F. M. Bufler, H. Mertens, R. Ritzenthaler, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

Mattan Kamon, Jérôme Mitard, Tom Schram, 2020, IEEE Transactions on Electron Devices.

Integration of a Stacked Contact MOL for Monolithic CFET

O. Richard, N. Horiguchi, K. Vandersmissen, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Recent advances in high-k dielectrics and inter layer engineering

Mikael Ostling, Eugenio Dentoni Litta, M. Ostling, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Enhanced Channel Mobility at Sub-nm EOT by Integration of a TmSiO Interfacial Layer in HfO2/TiN High-k/Metal Gate MOSFETs

M. Ostling, E. D. Litta, P. Hellstrom, 2015, IEEE Journal of the Electron Devices Society.

Integration of TmSiO/HfO 2 Dielectric Stack in Sub-nm EOT High- $k$ /Metal Gate CMOS Technology

Mikael Östling, Eugenio Dentoni Litta, Per-Erik Hellström, 2015 .

Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology

M. Östling, C. Henkel, P. Hellström, 2014 .

Effective workfunction control in TmSiO/HfO2 high-k/metal gate stacks

M. Ostling, P. Hellstrom, E. Litta, 2014, 2014 15th International Conference on Ultimate Integration on Silicon (ULIS).