M. Chen

High performance 90/65nm BEOL technology with CVD porous low-k dielectrics (k/spl sim/2.5) and low-k etching stop (k/spl sim/3.0)

M. Liang, W. Chang, S. Jang, 2003, IEEE International Electron Devices Meeting 2003.

Comparative study of physical and electrical characteristics of F- and C-doped low-K CVD oxides

W. Chang, S. Jeng, Z. Wu, 2001 .

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

W.-F. Wu, C. Wang, C. Su, 2017, 2017 Symposium on VLSI Technology.

Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide

H.J. Tao, S.C. Chen, M. Liang, 2006, IEEE Electron Device Letters.

Atomic Hydrogen Passivation Studies of Microcrystalline Phases in Ion-Implant Damaged Surface Layers of Silicon

S. Ashok, K. Srikanth, H. Chien, 1989 .

Advanced metal barrier free Cu damascene interconnects with PECVD silicon carbide barriers for 90/65-nm BEOL technology

M. Liang, S. Jang, Y.C. Lu, 2002, Digest. International Electron Devices Meeting,.