Kaname Teranishi

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor

Akira Fukuda, Koji Nii, Noriaki Sakamoto, 2013, IEEE Micro.

Design and evaluation of a digit‐parallel multiple‐valued content‐addressable memory

Michitaka Kameyama, Takahiro Hanyu, Kaname Teranishi, 1998 .

Multiple-valued floating-gate-MOS pass logic and its application to logic-in-memory VLSI

Michitaka Kameyama, Takahiro Hanyu, Kaname Teranishi, 1998, Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138).

Design and evaluation of a digit-parallel multiple-valued content-addressable memory

Michitaka Kameyama, Takahiro Hanyu, Kaname Teranishi, 1998, Systems and Computers in Japan.

Design of a Multiple-Valued Logic-in-Memory VLSI Using Floating-Gate MOS Transistors

Michitaka Kameyama, Takahiro Hanyu, Kaname Teranishi, 1998 .