M. Sumita

Mixed body-bias techniques with fixed Vt and Ids generation circuits

Y. Ikeda, S. Sakiyama, M. Sumita, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

A 800 MHz single cycle access 32 entry fully associative TLB with a 240 ps access match circuit

M. Sumita, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

A 100 Mhz Embedded Risc Microcontroller

Toru Kakiage, Y. Nishimichi, H. Yamashita, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

A 32-bit 64-word 9-read, 7-write ported, noise and process variation-tolerant and wide-voltage-range-operative register file using 130 nm technology

Y. Ikeda, M. Sumita, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

A 14:1 dynamic MUX FF with select activity detection

M. Sumita, T. Wada, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

Y. Ikeda, S. Sakiyama, M. Sumita, 2004, IEEE Journal of Solid-State Circuits.

A 400MHz 32b embedded microprocessor core AM34-1 with 4.0GB/s cross-bar bus switch for SoC

M. Sumita, T. Sakamoto, M. Nakajima, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 32b 64-word 9-read-port/7-write-port pseudo dual-bank register file using copied memory cells for a multi-threaded processor

Y. Ikeda, M. Sumita, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..