Seonghwan Cho

A highly integrated analog baseband transceiver featuring a 12-bit 180MSPS pipelined A/D converter for multi-channel wireless LAN

Jipeng Li, G. Manganaro, K. Gulati, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

Taeik Kim, Hyunik Kim, Seonghwan Cho, 2017, IEEE Journal of Solid-State Circuits.

Design considerations for distributed microsensor systems

W. Rabiner, A. Chandrakasan, J. Goodman, 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-µm CMOS

Junghyup Lee, Seonghwan Cho, Taekwang Jang, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation

Hyojun Kim, Seonghwan Cho, Youngwoo Jo, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

Seonghwan Cho, Dongin Kim, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 470-μw multi-modulus injection-locked frequency divider with division ratio of 2, 3, 4, 5 and 6 in 0.13-μm CMOS

Joonhee Lee, Seonghwan Cho, 2007, 2007 IEEE Asian Solid-State Circuits Conference.