Yamato Yuta

发表

Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding

Inoue Michiko, Yoneda Tomokazu, Satonaka Sayaka, 2016 .

An expanded Per-Test X-Fault Diagnosis Method for LSI Circuits

Nakamura Yusuke, Kajihara Seiji, Miyase Kohei, 2007 .

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test

Kajihara Seiji, Wen Xiaoqing, Yamato Yuta, 2016 .

Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2011 .

Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test

Inoue Michiko, Yoneda Tomokazu, Yamato Yuta, 2013 .

Delay fault injection framework based on logic simulation with zero delay model

Inoue Michiko, Yoneda Tomokazu, Yamato Yuta, 2016 .

High Reliable Memory Architecture with Adaptive Combination of Aging-Aware In-Field Self-Repair and ECC

Inoue Michiko, Sato Yasuo, Yamato Yuta, 2016 .

Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories

Inoue Michiko, Yoneda Tomokazu, Yamato Yuta, 2015 .

A Capture-Safe Test Generation Scheme for At-speed Scan Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2008 .

Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification

Kajihara Seiji, Miyase Kohei, Enokimoto Kazunari, 2011 .

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2007 .

Data volume reduction method for unknown value handling in built-in self test used in field

Inoue Michiko, Yoneda Tomokazu, Yamato Yuta, 2013 .

A Constrained Test Generation Method for Low Power Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2007 .