Katsuro Sasaki

发表

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Makoto Suzuki, Yoshinobu Nakagome, Toshiaki Yamanaka, 1993 .

A 1.5-V full-swing BiCMOS logic circuit

Kazuo Yano, Atsuo Watanabe, Takashi Nishida, 1992 .

Trends in low-power RAM circuit technologies

Y. Nakagome, Katsuro Sasaki, K. Itoh, 1995 .

Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry

Satoshi Tanaka, Hirotsugu Kojima, Katsuro Sasaki, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

Makoto Suzuki, Yoshinobu Nakagome, Toshiaki Yamanaka, 1995 .

A 1.7-V adjustable I/O interface for low-voltage fast SRAMs

Toshiaki Yamanaka, Katsuro Sasaki, Koichiro Ishibashi, 1992 .

A voltage down converter with submicroampere standby current for low-power static RAMs

Katsuro Sasaki, Koichiro Ishibashi, H. Toyoshima, 1992 .

Trends in low-power RAM circuit technologies

Y. Nakagome, Katsuro Sasaki, K. Itoh, 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

A 5.9pm2 SUPER LOW POWER SRAM CELL USING A NEW PHASE-SHIFT LITHOGRAPHY

Eiji Takeda, Norio Hasegawa, T. Nishida, 1990 .

TPM 8.3: A 23ns 4Mb CMOS SRAM with n.5t.tA Standby Current

Shojiro Asai, Shuji Ikeda, T. Masuhara, 1990 .

FA 13.2: A 7ns 140mW 1Mb CMOS SRAM with Current Sense Amplifier

Fumio Kojima, Toshiaki Yamanaka, Akihiro Shimizu, 1990 .

A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell

Toshiaki Yamanaka, K. Takasugi, N. Ohki, 1993 .

A 1-V TFT-load SRAM using a two-step word-voltage method

Toshiaki Yamanaka, K. Takasugi, Katsuro Sasaki, 1992 .

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Toshiaki Yamanaka, Katsuro Sasaki, Sadayuki Morita, 1994 .

Special Issue on Low-power LSIs and Technologies

Katsuro Sasaki, 2000 .

A 4.4-ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

Makoto Suzuki, Yoshinobu Nakagome, Akihiro Shimizu, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

A 1.7V Adjustable I/O Interface for Low Voltage Fast SRAMs

Koichiro Ishibashi, H. Toyoshima, Toshiaki Yamanaka, 1991, 1991 Symposium on VLSI Circuits.

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits

Y. Nakagome, Toshiaki Yamanaka, Katsuro Sasaki, 1994 .

Half-swing clocking scheme for 75% power saving in clocking circuitry

Satoshi Tanaka, Katsuro Sasaki, Hirotsugu Kojima, 1994 .

A 9 ns 1 Mb CMOS SRAM

S. Hanamura, Katsuhiro Shimohigashi, Toshiaki Yamanaka, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

Koichiro Ishibashi, H. Toyoshima, Toshiaki Yamanaka, 1992 .

Advanced TFT SRAM cell technology using a phase-shift lithography

Eiji Takeda, Norio Hasegawa, Koichiro Ishibashi, 1995 .

A 5.9 mu m/sup 2/ super low power SRAM cell using a new phase-shift lithography

Eiji Takeda, Norio Hasegawa, Koichiro Ishibashi, 1990, International Technical Digest on Electron Devices.