C. Vizioz

发表

3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

O. Rozeau, O. Faynot, T. Ernst, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Undercut elimination in DUV negative systems: application to lithography and etching of metal levels

Michel Heitzmann, Dominique Poncet, Bernard Previtali, 1996, Advanced Lithography.

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

O. Faynot, P. Batude, M. Vinet, 2016, 2016 IEEE Symposium on VLSI Technology.

Plasma etching and integration challenges using alternative patterning techniques for 11nm node and beyond

S. Barnola, R. Tiron, S. Barraud, 2014, Advanced Lithography.

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

Romain Wacquez, Maud Vinet, Marc Sanquer, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

M. Haond, T. Skotnicki, S. Monfray, 2002, Digest. International Electron Devices Meeting,.

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

O. Faynot, G. Ghibaudo, T. Ernst, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm

O. Faynot, M. Vinet, B. Previtali, 2010, 2010 Symposium on VLSI Technology.

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

O. Faynot, M. Casse, S. Barraud, 2012, IEEE Electron Device Letters.

Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications

Sylvain Maitrejean, Yves Morand, Maud Vinet, 2004 .

FDSOI nanowires: An opportunity for hybrid circuit with field effect and single electron transistors

O. Faynot, M. Vinet, L. Grenouillet, 2013, 2013 IEEE International Electron Devices Meeting.

Ultra-scaled high-frequency single-crystal Si NEMS resonators and their front-end co-integration with CMOS for high sensitivity applications

O. Rozeau, K. Benotmane, G. Cibrario, 2012, 2012 IEEE 25th International Conference on Micro Electro Mechanical Systems (MEMS).

Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight (invited)

Sylvain Barraud, P. Brianceau, T. Magis, 2011 .

3D stacked channels: how series resistances can limit 3D devices performance

F. Andrieu, T. Ernst, S. Deleonibus, 2007, 2007 IEEE International SOI Conference.

Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

O. Faynot, G. Ghibaudo, F. Andrieu, 2006, 2006 International Electron Devices Meeting.

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

X. Garros, O. Faynot, F. Andrieu, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

F. Andrieu, B. Previtali, S. Barraud, 2020, 2020 IEEE Symposium on VLSI Technology.

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- $\kappa$ Dielectrics, and Metallic Source/Drain

M. Vinet, D. Lafond, S. Deleonibus, 2009, IEEE Electron Device Letters.

Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

O. Rozeau, O. Faynot, M. Vinet, 2014, 2014 IEEE International Electron Devices Meeting.

Hydrogen annealing of arrays of planar and vertically stacked Si nanowires

Thomas Ernst, J. Foucher, C. Vizioz, 2007 .

Performance and design considerations for gate-all-around stacked-NanoWires FETs

O. Rozeau, M. Vinet, F. Andrieu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

3D Sequential Integration: Application-driven technological achievements and guidelines

X. Garros, O. Rozeau, O. Faynot, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

15nm-diameter 3D Stacked Nanowires with optional Independent Gates operation (?FET)

O. Faynot, Christian Arvet, S. Deleonibus, 2008 .

Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects

O. Faynot, G. Ghibaudo, F. Allain, 2013, 2013 Symposium on VLSI Technology.

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

G. Reimbold, O. Faynot, G. Ghibaudo, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

X. Garros, O. Faynot, Yves Campidelli, 2007 .

Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

O. Rozeau, M. Vinet, J. Lacord, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

/spl Omega/FETs transistors with TiN metal gate and HfO/sub 2/ down to 10nm

X. Garros, O. Faynot, M. Vinet, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Opportunities and challenges of nanowire-based CMOS technologies

O. Rozeau, M. Vinet, F. Allain, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires

O. Faynot, G. Ghibaudo, T. Ernst, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Single-mode waveguides for GRAVITY

A. Delboulbé, L. Jocou, Y. Magnard, 2018, Astronomy & Astrophysics.

Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

G. Ghibaudo, P. Leroux, C. Tabone, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

Bonded planar double-metal-gate NMOS transistors down to 10 nm

M. Vinet, D. Lafond, S. Deleonibus, 2005, IEEE Electron Device Letters.

Highly-performant 38 nm SON (silicon-on-nothing) P-MOSFETs with 9 nm-thick channels

M. Haond, T. Skotnicki, S. Monfray, 2002, 2002 IEEE International SOI Conference.

Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization

Simon Deleonibus, C. Carabasse, Thomas Ernst, 2008 .

3D nanowire gate-all-around transistors: Specific integration and electrical features

O. Faynot, S. Deleonibus, Gerard Ghibaudo, 2008 .

High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

X. Garros, G. Ghibaudo, M.-P. Samson, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

M. Haond, T. Skotnicki, S. Monfray, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors

X. Garros, G. Ghibaudo, D. Bosch, 2020, 2020 IEEE Symposium on VLSI Technology.

Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment

O. Faynot, M. Vinet, D. Lafond, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Strain-enhanced performance of Si-Nanowire FETs

Sylvain Barraud, Gilles Reimbold, Gerard Ghibaudo, 2013 .

Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

F. Andrieu, T. Ernst, S. Deleonibus, 2008, 2008 Symposium on VLSI Technology.

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

O. Rozeau, O. Faynot, M. Vinet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).