Tomokazu Yoneda

发表

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

Hideo Fujiwara, Tomokazu Yoneda, 2002, J. Electron. Test..

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects

Hideo Fujiwara, Tomokazu Yoneda, 2008, 2008 Design, Automation and Test in Europe.

Power-Constrained SOC Test Schedules through Utilization of Functional Buses

Fawnizu Azmadi Hussin, Hideo Fujiwara, Alex Orailoglu, 2006, 2006 International Conference on Computer Design.

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time

Fawnizu Azmadi Hussin, Hideo Fujiwara, Tomokazu Yoneda, 2008, IEICE Trans. Inf. Syst..

Design for consecutive transparency of RTL circuits

Hideo Fujiwara, Tomokazu Yoneda, 2002 .

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints

Hideo Fujiwara, Tomokazu Yoneda, Danella Zhao, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

VLSI Implementation of Function Module for Texture Mapping and Motion Compensation

Takao Onoye, Isao Shirakawa, Tomokazu Yoneda, 1998 .

DART—A Concept of In-field Testing for Enhancing System Dependability

Kazumi Hatayama, Tomokazu Yoneda, Yukiya Miura, 2019 .

Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)

Tomokazu Yoneda, Krishnendu Chakrabarty, Thomas Edison Yu, 2007 .

A memory grouping method for sharing memory BIST logic

Hideo Fujiwara, Tomokazu Yoneda, Masahide Miyazaki, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Memory block based scan-BIST architecture for application-dependent FPGA testing

Kazumi Hatayama, Tomokazu Yoneda, Michiko Inoue, 2014, FPGA.

EqSA: A Golden-IC Free Equal Power Self-Authentication for Hardware Trojan Detection

Tomokazu Yoneda, Mohammed Abdul Kader, Fakir Sharif Hossain, 2018, 2018 International Conference on Innovations in Science, Engineering and Technology (ICISET).

Faster-than-at-speed test for increased test quality and in-field reliability

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2011, 2011 IEEE International Test Conference.

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency

Hideo Fujiwara, Tomokazu Yoneda, Satoshi Ohtake, 2005, 14th Asian Test Symposium (ATS'05).

Partial Scan Approach for Secret Information Protection

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2009, 2009 14th IEEE European Test Symposium.

DART: Dependable VLSI test architecture and its implementation

Motoyuki Sato, Kotaro Shimamura, Kazumi Hatayama, 2012, 2012 IEEE International Test Conference.

Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2016, 2016 21th IEEE European Test Symposium (ETS).

Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions

Alex Orailoglu, Tomokazu Yoneda, Michiko Inoue, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing

Tomokazu Yoneda, Hideo Fujiwara, Michiko Inoue, 2010, 2010 28th VLSI Test Symposium (VTS).

NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints

Fawnizu Azmadi Hussin, Hideo Fujiwara, Tomokazu Yoneda, 2008, IEICE Trans. Inf. Syst..

Aging test strategy and adaptive test scheduling for SoC failure prediction

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Design for consecutive transparency method of RTL circuits

Hideo Fujiwara, Tomokazu Yoneda, 2006 .

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

Chia Yee Ooi, Hideo Fujiwara, Tomokazu Yoneda, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Delay Testing: Improving Test Quality and Avoiding Over-testing

Tomokazu Yoneda, Satoshi Ohtake, Seiji Kajihara, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Test pattern selection to optimize delay test quality with a limited size of test set

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2010, 2010 15th IEEE European Test Symposium.

A Scan-Based On-Line Aging Monitoring Scheme

Tomokazu Yoneda, Michiko Inoue, Hyunbean Yi, 2014 .

Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)

Fawnizu Azmadi Hussin, Hideo Fujiwara, Tomokazu Yoneda, 2006 .

Balanced Secure Scan: Partial Scan Approach for Secret Information Protection

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2011, J. Electron. Test..

Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing

Hideo Fujiwara, Dan Zhao, Tomokazu Yoneda, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A DFT method for core-based systems-on-a-chip based on consecutive testability

Hideo Fujiwara, Tomokazu Yoneda, 2001, Proceedings 10th Asian Test Symposium.

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2016, IEICE Trans. Inf. Syst..

An ECC-based memory architecture with online self-repair capabilities for reliability enhancement

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2015, 2015 20th IEEE European Test Symposium (ETS).

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

Kazumi Hatayama, Tomokazu Yoneda, Michiko Inoue, 2012, 2012 IEEE International Test Conference.

Area and time co-optimization for system-on-a-chip based on consecutive testability

Hideo Fujiwara, Tomokazu Yoneda, Tetsuo Uchiyama, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers

Hideo Fujiwara, Tomokazu Yoneda, Masahiro Imanishi, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints

Hideo Fujiwara, Tomokazu Yoneda, Danella Zhao, 2008, IEICE Trans. Inf. Syst..

TAM Design and Optimization for Transparency-Based SoC Test

Hideo Fujiwara, Tomokazu Yoneda, Tomoo Inoue, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

An efficient scan tree design for test time reduction

Patrick Girard, Hideo Fujiwara, Tomokazu Yoneda, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

Fawnizu Azmadi Hussin, Hideo Fujiwara, Alex Orailoglu, 2007, 2007 Asia and South Pacific Design Automation Conference.

Seed Ordering and Selection for High Quality Delay Test

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2010, 2010 19th IEEE Asian Test Symposium.

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips

Hideo Fujiwara, Tomokazu Yoneda, Masahide Miyazaki, 2006, IEICE Trans. Inf. Syst..

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips

Hideo Fujiwara, Krishnendu Chakrabarty, Tomokazu Yoneda, 2008, IEICE Trans. Inf. Syst..

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection

Alex Orailoglu, Tomokazu Yoneda, Michiko Inoue, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)

Krishnendu Chakrabarty, Tomokazu Yoneda, Hideo Fujiwara, 2007 .

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

Hideo Fujiwara, Krishnendu Chakrabarty, Tomokazu Yoneda, 2009, 2009 Asia and South Pacific Design Automation Conference.

Function Modules for Video Decoding and Computer Graphics

Takao Onoye, Isao Shirakawa, Tomokazu Yoneda, 1998 .

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints

Fawnizu Azmadi Hussin, Hideo Fujiwara, Tomokazu Yoneda, 2007, 12th IEEE European Test Symposium (ETS'07).

Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability

Hideo Fujiwara, Tomokazu Yoneda, Hisakazu Takakuwa, 2005, 14th Asian Test Symposium (ATS'05).

Test Pattern Ordering and Selection for High Quality Test Set under Constraints

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2012, IEICE Trans. Inf. Syst..

An ILP formulation for consecutive testability of system-on-a-chip

Hideo Fujiwara, Tomokazu Yoneda, 2002 .

Temperature-Variation-Aware Test Pattern Optimization

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2011, 2011 Sixteenth IEEE European Test Symposium.

Design for consecutive transparency of cores in system-on-a-chip

Hideo Fujiwara, Tomokazu Yoneda, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Serial and Parallel TAM Designs for System-on-Chip Interconnects Based on 2-Pattern Testability

Hideo Fujiwara, Tomokazu Yoneda, Yusuke Saga, 2004 .

Scheduling Power-Constrained Tests through the SoC Functional Bus

Fawnizu Azmadi Hussin, Hideo Fujiwara, Alex Orailoglu, 2008, IEICE Trans. Inf. Syst..

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue, 2017, Integr..

Design and Optimization of Transparency-Based TAM for SoC Test

Hideo Fujiwara, Tomokazu Yoneda, Tomoo Inoue, 2010, IEICE Trans. Inf. Syst..

A circuit failure prediction mechanism (DART) for high field reliability

Tomokazu Yoneda, Yukiya Miura, Satoshi Ohtake, 2009, 2009 IEEE 8th International Conference on ASIC.

Design for consecutive transparency method of RTL circuits

Hideo Fujiwara, Tomokazu Yoneda, 2006, Systems and Computers in Japan.

Test Scheduling for Multi-Clock Domain SoCs under Power Constraint

Hideo Fujiwara, Tomokazu Yoneda, Kimihiko Masuda, 2008, IEICE Trans. Inf. Syst..

A Failure Prediction Strategy for Transistor Aging

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reliability of ECC-based Memory Architectures with Online Self-repair Capabilities (ディペンダブルコンピューティング)

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2014 .

D-10-18 An Approach to Temperature Control During VLSI Test

Hideo Fujiwara, Tomokazu Yoneda, Satoshi Ohtake, 2009 .

Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units

Kazumi Hatayama, Tomokazu Yoneda, Michiko Inoue, 2014, 2014 IEEE 23rd Asian Test Symposium.

Power constrained IP core wrapper design with partitioned clock domains (信号処理)

Tomokazu Yoneda, Hideo Fujiwara, Danella Zhao, 2007 .

Power-Constrained Test Scheduling for Multi-Clock Domain SoCs

Hideo Fujiwara, Tomokazu Yoneda, Kimihiko Masuda, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A DFT Method for Time Expansion Model at Register Transfer Level

Hideo Fujiwara, Tomokazu Yoneda, Hiroyuki Iwata, 2007, 2007 44th ACM/IEEE Design Automation Conference.

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC

Fawnizu Azmadi Hussin, Hideo Fujiwara, Tomokazu Yoneda, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan

Tomokazu Yoneda, Michiko Inoue, Fakir Sharif Hossain, 2017, IEICE Trans. Inf. Syst..

Faster-ThanAt-Speed Test for Increased Test Quality and InField Reliability

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2015 .