N. Paras

Design and Integration of Vertical TFET and Memristor for Better Realization of Logical Functions

Jeetendra Singh, Shailendra Singh, N. Paras, 2022, Silicon.

Room temperature magento-electric coupling in Pb–Zn substituted Co2Y-hexaferrite

Deepika, A. Gaur, Anil Arya, 2022, Journal of Materials Science: Materials in Electronics.

Reaction ^{12}C(?,p^{-})^{12}N near the Threshold

A. Bernstein, E. Booth, W. Turchinetz, 1976 .

Inclusive Electroproduction of Low Energy Pi Mesons

P. Stoler, K. Blomqvist, J. Lerose, 1979 .

Electroproduction of charged pions from /sup 12/C leading to discrete final nuclear states

P. Stoler, A. Bernstein, K. Blomqvist, 1979 .

Pion Spectra to Individual Final States in the Reactions 12C(γ,π±)12B, 12N

P. Stoler, A. Bernstein, K. Blomqvist, 1979 .

A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications

S. S. Chauhan, N. Paras, 2019, Microelectronic Engineering.

Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs

S. S. Chauhan, N. Paras, 2019, Applied Physics A.

Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications

S. S. Chauhan, N. Paras, 2019, Microelectronic Engineering.

Design and Integration of Vertical TFET and Memristor for Better Realization of Logical Functions

Jeetendra Singh, Shailendra Singh, N. Paras, 2022, Silicon.

Investigation of the Direct Source to Drain Tunneling in 5 nm Nanotube Junctionless Field Effect Transistor

N. Paras, Manisha Bharti, Pramod Kumar Gautam, 2023, 2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS).

Optimization of Design Parameters for Vertical Tunneling Based Dual Metal Dual Gate TFET

S. S. Chauhan, N. Paras, 2019, 2019 International Conference on Advances in Computing and Communication Engineering (ICACCE).

Vertical Tunneling Based Tunnel Field Effect Transistor with Workfunction Engineered Hetero-Gate to Enhance DC Characteristics

S. S. Chauhan, N. Paras, 2019, Journal of Nanoelectronics and Optoelectronics.