Kyuchull Kim

Low-Area Wrapper Cell Design for Hierarchical SoC Testing

Kewal K. Saluja, Kyuchull Kim, 2009, J. Electron. Test..

On fault deletion problem in concurrent fault simulation for synchronous sequential circuits

Kewal K. Saluja, Kyuchull Kim, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

FUNCTIONAL VERIFICATION OF A SAFETY CLASS CONTROLLER FOR NPPS USING A UVM REGISTER MODEL

Kyuchull Kim, 2014 .

Improving Code Coverage for the FPGA Based Nuclear Power Plant Controller

Seungrohk Oh, Kyuchull Kim, Hyung-Suk Heo, 2014 .

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

Kewal K. Saluja, Kyuchull Kim, 1996 .

Testbench Implementation for FPGA based Nuclear Safety Class System using OVM

Seungrohk Oh, Kyuchull Kim, Hyung-Suk Heo, 2014 .

Fast computation of MISR signatures

Kewal K. Saluja, Manoj Franklin, Kyuchull Kim, 1995, Proceedings of the 8th International Conference on VLSI Design.

Improved test generation for high-activity circuits

Kewal K. Saluja, Kyuchull Kim, 1990, IEEE Design & Test of Computers.

CCSTG: an efficient test pattern generator for sequential circuits

Kewal K. Saluja, Kyuchull Kim, K. Saluja, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

HYSIM: Hybrid Fault Simulation for Synchronous

Kewal K. Saluja, Kyuchull Kim, 1996 .