PariVallal Kannan

On metrics for comparing routability estimation methods for FPGAs

Dinesh Bhatia, Shankar Balachandran, PariVallal Kannan, 2002, DAC '02.

NEBULA: A Partially and Dynamically Reconfigurable Architecture

Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, 1999, FPL.

On routing demand and congestion estimation for FPGAs

Dinesh Bhatia, Shankar Balachandran, PariVallal Kannan, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits

Dinesh Bhatia, Shankar Balachandran, PariVallal Kannan, 2001, FPL.

Interconnect estimation for FPGAs under timing driven domains

Dinesh Bhatia, PariVallal Kannan, 2003, Proceedings 21st International Conference on Computer Design.

Interconnect estimation for FPGAs

Dinesh Bhatia, PariVallal Kannan, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Estimating pre-placement FPGA interconnection requirements

Dinesh Bhatia, PariVallal Kannan, D. Bhatia, 2004, 17th International Conference on VLSI Design. Proceedings..

On metrics for comparing interconnect estimation methods for FPGAs

Dinesh Bhatia, Shankar Balachandran, PariVallal Kannan, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Rapid and Reliable Routability Estimation for FPGAs

Dinesh Bhatia, Shankar Balachandran, PariVallal Kannan, 2002, FPL.

REACT: Reactive Environment for Runtime Reconfiguration

Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, 1998, FPL.

Tightly Integrated Placement and Routing for FPGAs

Dinesh Bhatia, PariVallal Kannan, D. Bhatia, 2001, FPL.