Zule Xu

发表

Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error

Yasushi Fukuda, Zule Xu, Takayuki Kawahara, 2017, IEICE Trans. Electron..

A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving –66dBc Worst-Case In-Band Fractional Spur

Tetsuya Iizuka, Zule Xu, Masaru Osada, 2020, 2020 IEEE Symposium on VLSI Circuits.

Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs

Akira Matsuzawa, Zule Xu, Mitsutoshi Sugawara, 2017, IEICE Trans. Electron..

An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration

Yun Wang, Rui Wu, Bangan Liu, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

A 0.8 ps-LSB, 10-bit, 0.018 mm 2 Time-to-Digital Converter

Akira Matsuzawa, Zule Xu, 松澤昭, 2014 .

A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier

Akira Matsuzawa, Zule Xu, James Lin, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

Kenichi Okada, Akira Matsuzawa, Zule Xu, 2016, IEEE Journal of Solid-State Circuits.

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2017, IEICE Trans. Electron..

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS

Naoki Ojima, Tetsuya Iizuka, Zule Xu, 2019, 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS).

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers

Zule Xu, Jun Gyu Lee, Shoichi Masui, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 2 GHz 3.1 mW type-I digital ring-based PLL

Kenichi Okada, Akira Matsuzawa, Zule Xu, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC

Akira Matsuzawa, Zule Xu, Seungjong Lee, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design

Zule Xu, Takayuki Kawahara, 2017, IEICE Trans. Electron..

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool

Toru Nakura, Tetsuya Iizuka, Zule Xu, 2019, IEICE Electron. Express.

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC

Akira Matsuzawa, Zule Xu, Seungjong Lee, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector

Akira Matsuzawa, Zule Xu, Kenichi Okada, 2019, IEICE Trans. Electron..

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell

Kenichi Okada, Akira Matsuzawa, Zule Xu, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

Zule Xu, Jun Gyu Lee, Shoichi Masui, 2011, IEICE Trans. Electron..

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Zule Xu, Shuowei Li, Naoki Ojima, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Picosecond Resolution Time-to-Digital Converter Using ${{\rm G}_{\rm m}} \hbox{-C}$ Integrator and SAR-ADC

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2014, IEEE Transactions on Nuclear Science.

A Varactor-Less and Dither-Less LC-Digitally Controlled Oscillator with 9-bit Fine Bank, 0.26 mm 2 Area, and 6.7 kHz Frequency Resolution

Akira Matsuzawa, Zule Xu, Mitsutoshi Sugawara, 2014 .

Picosecond Resolution Time-to-Digital Converter Using G mC Integrator and SAR-ADC

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2022 .