T. Francis

High strain embedded-SiGe via low temperature reduced pressure chemical vapor deposition

A. Reznicek, D. Sadana, T. Adam, 2012 .

Case of via resistance increase during thermal cycle

T. Francis, S. Drizlikh, 2004, 2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530).

Moisture requirements to reduce interfacial sub-oxides and lower hydrogen pre-bake temperatures for RPCVD Si epitaxy

R. Torres, M. Raynor, P. Brabant, 2013 .

Thermal budget reduction and throughput enhancement for CMOS Epi stressors via wet clean interface contamination evaluation and control

Mark A. Wirzbicki, D. Sadana, P. Brabant, 2011, 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.