Sunhae Shin

Multi-Valued Logic Based on CMOS Technology

Jae Won Jung, Kyung Rok Kim, Sunhae Shin, 2015 .

CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits

Jae Won Jeong, Kyung Rok Kim, Sunhae Shin, 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).

Tunnel Junction-Embedded Field-Effect Transistor for Negative Differential Resistance and Its Multi-Valued Logic and Memory Applications

Sunhae Shin, 2013 .

Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-k Spacer Technology

Jae Won Jeong, Kyung Rok Kim, Sunhae Shin, 2018 .

Ultra-Low Power Ternary CMOS Platform for Physical Synthesis of Multi-Valued Logic and Memory Applications

Sunhae Shin, 2017 .

Novel tri-state latch using single-peak negative differential resistance devices

Kyung Rok Kim, Sunhae Shin, 2014, 2014 Silicon Nanoelectronics Workshop (SNW).

Demonstration of standrad ternary inverter based on CMOS technology

Jae Won Jeong, Kyung Rok Kim, Sunhae Shin, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

Novel design of multiple negative-differential resistance (NDR) device in a 32nm CMOS technology using TCAD

Kyung Rok Kim, Sunhae Shin, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A Novel Ternary Multiplier Based on Ternary CMOS Compact Model

Seokhyeong Kang, Jaewoo Kim, Sunmin Kim, 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).

Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology

Sunhae Shin, Esan Jang, Jae Won Jung, 2015 .