Luca Sterpone

发表

Anexperimental analysi sofhardening techniques forSRAM-based FPGAs

Massimo Violante, Luca Sterpone, S. Rezgui, 2005 .

A Fault Injection Environment for SoPC's Embedded Microprocessors

Massimo Violante, Luca Sterpone, Marta Portela-Garcia, 2006, Latin American Test Workshop - LATW.

An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs

Ludovica Bozzoli, Luca Sterpone, 2020, IEEE Access.

Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

Heinrich Theodor Vierhaus, Robért Glein, Florian Rittner, 2014, 2014 19th IEEE European Test Symposium (ETS).

A graph-based representation of Gene Expression profiles in DNA microarrays

Alfredo Benso, Gianfranco Politano, Stefano Di Carlo, 2008, 2008 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology.

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

Luca Sterpone, Marco Desogus, David Merodio Codinachs, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

Online Test of Control Flow Errors: A New Debug Interface-Based Approach

Matteo Sonza Reorda, Luis Entrena, Luca Sterpone, 2016, IEEE Transactions on Computers.

Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets

Matteo Sonza Reorda, Luca Sterpone, Josie E. Rodriguez Condia, 2020, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs

Luca Sterpone, David Merodio Codinachs, Boyang Du, 2017, ACM Great Lakes Symposium on VLSI.

Validation and robustness assessment of an automotive system

Matteo Sonza Reorda, Luca Sterpone, Marco Sabatini, 2013, 2013 8th IEEE Design and Test Symposium.

On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA

Ludovica Bozzoli, Luca Sterpone, Boyang Du, 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

Niccolò Battezzati, Massimo Violante, Chiara Sandionigi, 2010, 2010 15th IEEE European Test Symposium.

Digital Design Techniques for Dependable High Performance Computing

Luca Sterpone, Sarah Azimi, 2020, 2020 IEEE International Test Conference (ITC).

SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up

Luca Sterpone, L. Sterpone, 2013, Microelectron. Reliab..

Radiation-induced SET on Flash-based FPGAs: Analysis and Filtering methods

Luca Sterpone, Sarah Azimi, 2017 .

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs

Andrea Domenici, Luca Sterpone, Cinzia Bernardeschi, 2013, ACM Great Lakes Symposium on VLSI.

System-Level Considerations

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

On the optimal design of triple modular redundancy logic for SRAM-based FPGAs

Luigi Carro, Matteo Sonza Reorda, Fernanda Gusmão de Lima Kastensmidt, 2005, Design, Automation and Test in Europe.

Reconfigurable Field Programmable Gate Arrays: Failure Modes and Analysis

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs

Andrea Domenici, Luca Sterpone, Cinzia Bernardeschi, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs

Luca Sterpone, David Merodio Codinachs, Boyang Du, 2018, 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

Luigi Carro, Massimo Violante, Matteo Sonza Reorda, 2007, J. Electron. Test..

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Ernesto Sánchez, Luca Sterpone, Anees Ullah, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

Ernesto Sánchez, Luca Sterpone, Carles Ferrer, 2017, Microelectron. Reliab..

Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results

Luigi Carro, Matteo Sonza Reorda, Luca Sterpone, 2014, Microelectron. Reliab..

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems

Matteo Sonza Reorda, Luca Sterpone, Anees Ullah, 2017, IEEE Transactions on Computers.

Simulation-based analysis of SEU effects in SRAM-based FPGAs

D. Bortolato, M. Ceschia, Massimo Violante, 2004 .

On the evaluation of SEU effects in GPGPUs

Matteo Sonza Reorda, Luca Sterpone, Boyang Du, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Reconfigurable Field Programmable Gate Arrays: Hardening Solutions

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

Radiation-induced Single Event Transient effects during the reconfiguration process of SRAM-based FPGAs

Ludovica Bozzoli, Luca Sterpone, Boyang Du, 2019 .

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders

Salvatore Pontarelli, Adelio Salsano, Massimo Violante, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs

Ludovica Bozzoli, Luca Sterpone, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Fault injection in GPGPU cores to validate and debug robust parallel applications

Luigi Carro, Matteo Sonza Reorda, Luca Sterpone, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs

Luca Sterpone, Anees Ullah, 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

Online monitoring soft errors in reconfigurable FPGA during radiation test

Luca Sterpone, Boyang Du, 2017, 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC).

A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices

Massimo Violante, Luca Sterpone, Niccolo Battezzati, 2008, WREFT '08.

A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs

Luca Sterpone, Carles Ferrer, Anees Ullah, 2017, J. Syst. Archit..

Putting Mitigation Techniques at Work

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs

Niccolò Battezzati, Luca Sterpone, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation

Dan Alexandrescu, Luca Sterpone, Celia López-Ongil, 2014, 2014 19th IEEE European Test Symposium (ETS).

Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

Steven M. Guertin, David Kaeli, Luis Entrena, 2015, IEEE Transactions on Nuclear Science.

A new RC design for mixed-grain based dynamically reconfigurable architectures

Luigi Carro, Luca Sterpone, Eduardo Luis Rhod, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

A new decompression system for the configuration process of SRAM-based FPGAS

Massimo Violante, Luca Sterpone, M. Violante, 2007, GLSVLSI '07.

Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs

Luca Sterpone, Fernanda Lima Kastensmidt, Jimmy Tarrillo, 2016 .

The Use of Benchmarks for High-Reliability Systems

David Kaeli, Matteo Sonza Reorda, Luis Entrena, 2015 .

ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications

Massimo Violante, Luca Sterpone, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

A New Soft-Error Resilient Voltage-Mode Quaternary Latch

Luigi Carro, Luca Sterpone, Eduardo Luis Rhod, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

Luca Sterpone, Hipólito Guzmán-Miranda, Jonathan Noel Tombs, 2008, 2008 Design, Automation and Test in Europe.

Fault Injection-based Reliability Evaluation of SoPCs

Massimo Violante, Matteo Sonza Reorda, Luis Entrena, 2006, Eleventh IEEE European Test Symposium (ETS'06).

Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment

Luca Sterpone, Boyang Du, Sarah Azimi, 2017, J. Syst. Archit..

Soft error effects analysis and mitigation in VLIW safety-critical applications

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Dependability evaluation of transient fault effects in reconfigurable compute fabric devices

Massimo Violante, Luca Sterpone, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

On the development of Software-Based Self-Test methods for VLIW processors

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures

Ludovica Bozzoli, Luca Sterpone, 2019, ARC.

Radiation-induced single event transients modeling and testing on nanometric flash-based technologies

Luca Sterpone, Boyang Du, Sarah Azimi, 2015, Microelectron. Reliab..

Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach

Ludovica Bozzoli, Luca Sterpone, 2018, ARC.

Exploiting the debug interface to support on-line test of control flow errors

Matteo Sonza Reorda, Luis Entrena, Luca Sterpone, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Effective Characterization of Radiation-induced SET on Flash-based FPGAs

Luca Sterpone, Sarah Azimi, 2017, 2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

Luca Sterpone, Mario Porrmann, Jens Hagemeyer, 2018, IEEE Transactions on Emerging Topics in Computing.

On the evaluation of soft-errors detection techniques for GPGPUs

Luigi Carro, Matteo Sonza Reorda, Luca Sterpone, 2013, 2013 8th IEEE Design and Test Symposium.

A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's

Niccolò Battezzati, Luca Sterpone, 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

A design flow for protecting FPGA-based systems against single event upsets

Massimo Violante, Luca Sterpone, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Gene expression reliability estimation through cluster-based analysis

Alfredo Benso, Stefano Di Carlo, Gianfranco Politano, 2009, 2009 IEEE International Workshop on Medical Measurements and Applications.

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Dan Alexandrescu, Thomas Lange, Ludovica Bozzoli, 2018, 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience

Luca Sterpone, Mario Porrmann, Jens Hagemeyer, 2013 .

Analysis of SEU effects in partially reconfigurable SoPCs

Fabio Margaglia, Luca Sterpone, Mario Porrmann, 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs

Luca Sterpone, David Merodio Codinachs, Boyang Du, 2016, 2016 21th IEEE European Test Symposium (ETS).

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs

Alessandro Paccagnella, Massimo Violante, Luca Sterpone, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

A dynamic reconfiguration mechanism to increase the reliability of GPGPUs

Matteo Sonza Reorda, Luca Sterpone, Josie E. Rodriguez Condia, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs

Luca Sterpone, 2010, TRETS.

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

Luca Sterpone, Luca Boragno, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs

Luca Sterpone, Matteo Sonza Reorda, Josie E. Rodriguez Condia, 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Analysis of Radiation-induced SETs in 3D VLSI Face-to-Back LUTs

Ludovica Bozzoli, Luca Sterpone, Boyang Du, 2019 .

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Cecilia Metra, Marco Ottavi, Salvatore Pontarelli, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA

Luca Sterpone, Boyang Du, Cesar Boatella Polo, 2019, IEEE Transactions on Nuclear Science.

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs

Massimo Violante, Fernanda Gusmão de Lima Kastensmidt, Luca Sterpone, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Efficient estimation of SEU effects in SRAM-based FPGAs

Massimo Violante, Matteo Sonza Reorda, Luca Sterpone, 2005, 11th IEEE International On-Line Testing Symposium.

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs

Luca Sterpone, David Merodio Codinachs, Boyang Du, 2019, Integr..

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2012, VLSI-SoC.

Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs

Ludovica Bozzoli, Luca Sterpone, 2020, ARC.

Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips

Massimo Violante, Luca Sterpone, Francesco Abate, 2008 .

An Emulation Platform for Evaluating the Reliability of Deep Neural Networks

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2020, 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs

Massimo Violante, Luca Sterpone, 2007, 12th IEEE European Test Symposium (ETS'07).

A novel scalable and reconfigurable emulation platform for embedded systems verification

Matteo Sonza Reorda, Luca Sterpone, Marco Sabatini, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Reconfigurable Field Programmable Gate Arrays: Basic Concepts

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

On the Analysis of Radiation-induced Failures in the AXI Interconnect Module

Luca Sterpone, Sarah Azimi, C. De Sio, 2020 .

Optimization of Self Checking FIR filters by means of Fault Injection Analysis

Salvatore Pontarelli, Adelio Salsano, Massimo Violante, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing

Luca Sterpone, Mario Porrmann, Jens Hagemeyer, 2013, IEEE Transactions on Computers.

A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs

Ludovica Bozzoli, Luca Sterpone, Boyang Du, 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

On the Evaluation of the PIPB Effect within SRAM-based FPGAs

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2019, 2019 IEEE European Test Symposium (ETS).

Combined software and hardware techniques for the design of reliable IP processors

Massimo Violante, Maurizio Rebaudengo, Donatella Sciuto, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs

Andrea Domenici, Luca Sterpone, Cinzia Bernardeschi, 2016, Integr..

On-line testing of permanent radiation effects in reconfigurable systems

Luca Sterpone, Mario Porrmann, Jens Hagemeyer, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Scalable FPGA graph model to detect routing faults

Luca Sterpone, Gianpiero Cabodi, Boyang Du, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

New evolutionary techniques for test-program generation for complex microprocessor cores

Giovanni Squillero, Massimo Violante, Matteo Sonza Reorda, 2005, GECCO '05.

Differential gene expression graphs: A data structure for classification in DNA microarrays

Alfredo Benso, Gianfranco Politano, Stefano Di Carlo, 2008, 2008 8th IEEE International Conference on BioInformatics and BioEngineering.

An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques

Pedro Reviriego, Juan Antonio Maestro, Luca Sterpone, 2007 .

Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs

Luca Sterpone, 2009, ARC.

Soft errors in Flash-based FPGAs: Analysis methodologies and first results

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2009, 2009 International Conference on Field Programmable Logic and Applications.

A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network

Ludovica Bozzoli, Luca Sterpone, Artur Jutman, 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

On the development of diagnostic test programs for VLIW processors

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

COMET: a Configuration Memory Tool to Analyze, Visualize and Manipulate FPGAs Bitstream

Ludovica Bozzoli, Luca Sterpone, 2018 .

Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs

Luca Sterpone, Sarah Azimi, Annarita Moramarco, 2017, 2017 IEEE 26th International Symposium on Industrial Electronics (ISIE).

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques

Dan Alexandrescu, Luca Sterpone, Thomas Lange, 2019, 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks – Supplemental Volume (DSN-S).

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Dan Alexandrescu, Luca Sterpone, Thomas Lange, 2019, 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Fault-Tolerance Techniques for Soft-Core Processors Using the Trace Interface

Matteo Sonza Reorda, Luis Entrena, Luca Sterpone, 2016 .

On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs

Luca Sterpone, David Merodio Codinachs, Boyang Du, 2015, 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture

Luca Sterpone, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

A probe-based SEU detection method for SRAM-based FPGAs

Luca Sterpone, Luca Boragno, 2017, Microelectron. Reliab..

Accurate Mitigation of Single Event Effects on Flash-based FPGAs: A new Design Flow

Luca Sterpone, Boyang Du, D. Merodio Codinachs, 2013 .

Hybrid soft error mitigation techniques for COTS processor-based systems

Sergio Cuenca-Asensi, Eduardo Chielle, Matteo Sonza Reorda, 2016, 2016 17th Latin-American Test Symposium (LATS).

PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing

Ludovica Bozzoli, Luca Sterpone, Cinzia Bernardeschi, 2018, 2018 International Symposium on Rapid System Prototyping (RSP).

Multiple errors produced by single upsets in FPGA configuration memory: a possible solution

Massimo Violante, Matteo Sonza Reorda, Luca Sterpone, 2005, European Test Symposium (ETS'05).

Advanced technologies for transient faults detection and compensation

Massimo Violante, Matteo Sonza Reorda, Luca Sterpone, 2011 .

Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications

Florian Dittmann, Fabio Margaglia, Luca Sterpone, 2011 .

A scalable platform for run-time reconfigurable satellite payload processing

Florian Dittmann, Fabio Margaglia, Ulrich Rückert, 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

A Low-Cost Emulation System for Fast Co-verification and Debug

Matteo Sonza Reorda, Marco Sabatini, Luca Sterpone, 2011, 2011 Sixteenth IEEE European Test Symposium.

A Zero-Timing Overhead SET Mitigation Approach for Flash-based FPGAs

Luca Sterpone, Boyang Du, Sarah Azimi, 2018 .

A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA

Luca Sterpone, Boyang Du, Sarah Azimi, 2017, Microelectron. Reliab..

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs

Luca Sterpone, Boyang Du, L. Sterpone, 2015, ARC.

Analysis and mitigation of single event effects on flash-based FPGAS

Luca Sterpone, Boyang Du, 2014, 2014 19th IEEE European Test Symposium (ETS).

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques

Pedro Reviriego, Juan Antonio Maestro, Luca Sterpone, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

FlexGripPlus: An improved GPGPU model to support reliability analysis

Matteo Sonza Reorda, Luca Sterpone, Boyang Du, 2020, Microelectronics Reliability.

A New Fault Injection Approach for Testing Network-on-Chips

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2012, 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing.

Self rerouting of dynamically reconfigurable SRAM-based FPGAs

Ludovica Bozzoli, Luca Sterpone, L. Sterpone, 2017, 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs

Luigi Carro, Stephan Wong, Debora Matos, 2011, 2011 Design, Automation & Test in Europe.

On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs

Niccolò Battezzati, Alessandro Paccagnella, Massimo Violante, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Electronics System Design Techniques for Safety Critical Applications

Luca Sterpone, 2009, Lecture Notes in Electrical Engineering.

On the mitigation of SET broadening effects in integrated circuits

Niccolò Battezzati, Luca Sterpone, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Hardening FPGA-based Systems Against SEUs: A New Design Methodology

Massimo Violante, Luca Sterpone, 2006, J. Comput..

Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect

Luca Sterpone, Boyang Du, Sarah Azimi, 2019, IEEE Access.

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Analysis and mitigation of SEUs in ARM-based SoC on Xilinx Virtex-V SRAM-based FPGAs

Luca Sterpone, Marco Desogus, Boyang Du, 2015, 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices

Gian Carlo Cardarilli, Salvatore Pontarelli, Adelio Salsano, 2007 .

In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

Dan Alexandrescu, Luca Sterpone, Thomas Lange, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Improving GPU register file reliability with a comprehensive ISA extension

Luca Sterpone, Jose Rodrigo Azambuja, Marcio M. Goncalves, 2020 .

Fault injection analysis of transient faults in clustered VLIW processors

Matteo Sonza Reorda, Luca Sterpone, Salvatore Campagna, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

On the Evaluation of SEU Effects on AXI Interconnect Within AP-SoCs

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2020, ARCS.

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2014 .

Reprogrammable FPGAs for Mission-Critical Applications

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

Partition-Based Faults Diagnosis of a VLIW Processor

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2013, VLSI-SoC.

On the optimized generation of Software-Based Self-Test programs for VLIW processors

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs

Massimo Violante, Luca Sterpone, Miguel A. Aguirre, 2011, IEEE Transactions on Industrial Electronics.

A new approach to compress the configuration information of programmable devices

Guido Masera, Massimo Violante, Luca Sterpone, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Massimo Violante, Luca Sterpone, M. Violante, 2006, IEEE Transactions on Computers.

FPGA PAL Design Tools

Luca Sterpone, 2008, Wiley Encyclopedia of Computer Science and Engineering.

On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs

Luca Sterpone, Boyang Du, Sarah Azimi, 2018, Microelectron. Reliab..

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

Andrea Domenici, Luca Sterpone, Cinzia Bernardeschi, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

On the evaluation of SEU sensitiveness in SRAM-based FPGAs

Paolo Bernardi, Massimo Violante, Matteo Sonza Reorda, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

A new hardware architecture for performing the gridding of DNA microarray images

Massimo Violante, Luca Sterpone, M. Violante, 2007, GLSVLSI '07.

An FPGA-based testing platform for the validation of automotive powertrain ECU

Luca Sterpone, Boyang Du, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Software and Hardware Techniques for SEU Detection in IP Processors

Massimo Violante, Donatella Sciuto, Luca Sterpone, 2008, J. Electron. Test..

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

Dan Alexandrescu, Luca Sterpone, Maximilien Glorieux, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

A new solution to on-line detection of Control Flow Errors

Matteo Sonza Reorda, Luis Entrena, Luca Sterpone, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

Fault tolerant electronic system design

Luca Sterpone, Boyang Du, L. Sterpone, 2017, 2017 IEEE International Test Conference (ITC).

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU

Luca Sterpone, Matteo Sonza Reorda, Jose Rodrigo Azambuja, 2020, 2020 IEEE Latin-American Test Symposium (LATS).

A new SBST algorithm for testing the register file of VLIW processors

Matteo Sonza Reorda, Luca Sterpone, Davide Sabena, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images

Luca Sterpone, L. Sterpone, 2009, IEEE Transactions on Instrumentation and Measurement.

On the prediction of radiation-induced SETs in flash-based FPGAs

Luca Sterpone, Boyang Du, Sarah Azimi, 2016, Microelectron. Reliab..

On the mitigation of single event transients on flash-based FPGAs

Luca Sterpone, Boyang Du, Sarah Azimi, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

About the functional test of the GPGPU scheduler

Matteo Sonza Reorda, Luca Sterpone, Boyang Du, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2020, 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS).

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems

Dan Alexandrescu, Heinrich Theodor Vierhaus, Zoya Dyka, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs

Luca Sterpone, Anees Ullah, 2014, J. Electron. Test..

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture

Luca Sterpone, Davide Sabena, Mario Porrmann, 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach

Luca Sterpone, Sarah Azimi, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Analysis of radiation-induced SEUs on dynamic reconfigurable systems

Luca Sterpone, David Merodio Codinachs, Luca Boragno, 2016, 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs

Luca Sterpone, Boyang Du, Sarah Azimi, 2016, ARCS.

A New Domains-based Isolation Design Flow for Reconfigurable SoCs

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2021, 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS).

On the Evaluation of SEEs on Open-Source Embedded Static RAMs

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2021, 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC).

A Neutron Generator Testing Platform for the Radiation Analysis of SRAM-based FPGAs

Ludovica Bozzoli, Luca Sterpone, Boyang Du, 2021, 2021 IEEE International Instrumentation and Measurement Technology Conference (I2MTC).

A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability

Matteo Sonza Reorda, Luca Sterpone, Josie E. Rodriguez Condia, 2021, J. Supercomput..

An Automated Continuous Integration Multitest Platform for Automotive Systems

Luca Sterpone, Davide Sabena, Boyang Du, 2021 .

SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor

Luca Sterpone, Sarah Azimi, Corrado De Sio, 2021, 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories

Ludovica Bozzoli, Luca Sterpone, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Microvesicles Derived from Adult Human Bone Marrow and Tissue Specific Mesenchymal Stem Cells Shuttle Selected Pattern of miRNAs

Luca Sterpone, Ciro Tetta, Giovanni Camussi, 2010, PloS one.

Rad-Ray: A new Simulation Tool for the Analysis of Heavy Ions-induced SETs on ICs

Luca Sterpone, Boyang Du, Sarah Azimi, 2019 .

Power Consumption Versus Configuration SEUs in Xilinx Virtex-5 FPGAs

Massimo Violante, Luca Sterpone, Vincenzo Izzo, 2013, IEEE Transactions on Nuclear Science.