Claude Thibeault

发表

On the comparison of /spl Delta/I/sub DDQ/ and I/sub DDQ/ testing

Claude Thibeault, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Fast Polar Decoders: Algorithm and Implementation

Alexander Vardy, Warren J. Gross, Claude Thibeault, 2013, IEEE Journal on Selected Areas in Communications.

High-Speed Decoders for Polar Codes

Warren J. Gross, Claude Thibeault, Pascal Giard, 2017, Springer International Publishing.

Test quality of hierarchical defect-tolerant integrated circuits

Yvon Savaria, Claude Thibeault, Jean-Louis Houle, 1992, J. Electron. Test..

A hardware prototype for integration, test and validation of avionic networks

Yvon Savaria, Claude Thibeault, Guchuan Zhu, 2013, 2013 IEEE/AIAA 32nd Digital Avionics Systems Conference (DASC).

Partitioned successive-cancellation list decoding of polar codes

Alexios Balatsoukas-Stimming, Warren J. Gross, Claude Thibeault, 2015, 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

A Fast Software Polar Decoder pdf

Warren J. Gross, Claude Thibeault, Gabi Sarkis, 2013, ArXiv.

On new current signatures and adaptive test technique combination

Claude Thibeault, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques

Ghyslain Gagnon, Claude Thibeault, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Increasing the speed of polar list decoders

Alexander Vardy, Warren J. Gross, Claude Thibeault, 2014, 2014 IEEE Workshop on Signal Processing Systems (SiPS).

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Alexios Balatsoukas-Stimming, Philippe Flatresse, Warren J. Gross, 2017, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Automatic verification methodology based on structural test patterns

Claude Thibeault, Christelle Hobeika, Jean Francois Boland, 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.

Are defected-tolerant circuits with redundancy really cost-effective?

Claude Thibeault, Yvon Savaria, Y. Gagnon, 1997 .

Functional Constraint Extraction From Register Transfer Level for ATPG

Claude Thibeault, Christelle Hobeika, Jean-François Boland, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Panel Summaries

Yvon Savaria, Yervant Zorian, André Ivanov, 1996, IEEE Des. Test Comput..

Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis

Yves Blaquière, Claude Thibeault, Raoul Velazco, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

Detection and location of embedded critical paths by signal processing of IDD

Claude Thibeault, 1995 .

Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking

Yvon Savaria, Claude Thibeault, Otmane Aït Mohamed, 2013, FTSCS.

Flight Control Fault Models Based on SEU Emulation

Maarouf Saad, Claude Thibeault, Yves Audet, 2013 .

A True Glitch Masking Circuitry

Claude Thibeault, Jean Belzile, René Gagné, 2013 .

Unrolled Polar Decoders, Part II: Fast List Decoders pdf

Alexander Vardy, Warren J. Gross, Claude Thibeault, 2015, ArXiv.

Proceedings of the IEEE VLSI Test Symposium: Foreword

Yiorgos Makris, Claude Thibeault, Y. Makris, 2014, IEEE VLSI Test Symposium.

FPGAs as a proof of concept toward ASICs: a case study

Claude Thibeault, P. Longtin, J. M. Love, 1998 .

A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations

Claude Thibeault, Guy Bégin, 1999, IEEE Trans. Computers.

On the Susceptibility of SRAM-Based FPGA Routing Network to Delay Changes Induced by Ionizing Radiation

Claude Thibeault, Yves Audet, Yves Blaquière, 2019, IEEE Transactions on Nuclear Science.

Asynchronous component implementation methodology for GALS design in FPGAs

Claude Thibeault, Jean Belzile, Rene Gagne, 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.

Increasing current testing resolution

Claude Thibeault, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

A 0.35∼6.25 GHz cognitive radio frequency synthesizer architecture

Wessam Ajib, Claude Thibeault, Frederic Nabki, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Modeling and Dynamic Scheduling of Turbo Decoding for a Homogeneous Multiprocessor Platform

Yvon Savaria, Claude Thibeault, Francois Gagnon, 2008 .

A multi-Gbps unrolled hardware list decoder for a systematic polar code

Alexios Balatsoukas-Stimming, Andreas Peter Burg, Warren J. Gross, 2016, 2016 50th Asilomar Conference on Signals, Systems and Computers.

A new delay testing signal scheme robust to power distribution network impedance variation

Claude Thibeault, Ali Louati, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Autogenerating software polar decoders

Warren J. Gross, Claude Thibeault, Gabi Sarkis, 2014, 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP).

An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs

Yves Blaquière, Claude Thibeault, Raoul Velazco, 2015, 2015 IEEE East-West Design & Test Symposium (EWDTS).

Can the current behavior of faulty and fault-free ICs and the impact on diagnosis

Claude Thibeault, Luc Boisvert, C. Thibeault, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits

Yvon Savaria, Claude Thibeault, Jean-Louis Houle, 1992, J. Circuits Syst. Comput..

AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology

Yvon Savaria, François Gagnon, Claude Thibeault, 2019, 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

Fast software polar decoders

Warren J. Gross, Claude Thibeault, Gabi Sarkis, 2014, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

A New Yield Formula for Fault-Tolerant Large-Area Devices

Claude Thibeault, Jean-Louis Houle, Y. Savaria, 1989 .

An histogram based procedure for current testing of active defects

Claude Thibeault, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

On Faster IDDQ Measurements

Claude Thibeault, 2003, J. Electron. Test..

Illegal state extraction from Register Transfer Level

Claude Thibeault, Christelle Hobeika, Jean Francois Boland, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

A cost model for VLSI/MCM systems

Yvon Savaria, Claude Thibeault, Michel Kafrouni, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations pdf

Yvon Savaria, Claude Thibeault, Yves Audet, 2014, ArXiv.

Multi-abstraction level signature generation and comparison based on radiation single event upset

Claude Thibeault, Yves Audet, Christelle Hobeika, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

Impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits

Claude Thibeault, Jean-Louis Houle, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

Design of an actuator fault tolerant flight control system using fault detection and diagnosis

Maarouf Saad, Claude Thibeault, Jean-François Boland, 2013 .

Efficient identification of Faces in video Streams using low-Power Multi-Core Devices

Yvon Savaria, Claude Thibeault, Eric Granger, 2016, Handbook of Pattern Recognition and Computer Vision.

Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA

Yvon Savaria, Claude Thibeault, Fatima Zahra Tazi, 2016, 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

Applied Actuator Fault Accommodation in Flight Control Systems Using Fault Reconstruction Based FDD and SMC Reconfiguration

Maarouf Saad, Claude Thibeault, Jean-François Boland, 2014 .

Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model

Yvon Savaria, Claude Thibeault, Michel Meunier, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Fast List Decoders for Polar Codes

Alexander Vardy, Warren J. Gross, Claude Thibeault, 2015, IEEE Journal on Selected Areas in Communications.

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

Claude Thibeault, Christelle Hobeika, Yassine Hariri, 2012, J. Electron. Test..

A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures

Claude Thibeault, C. Thibeault, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

On extra combinational delays in SRAM FPGAs due to radiations

Claude Thibeault, Y. Savaria, Yves Audet, 2012 .

IEEE VLSI Test Symposium : meeting the quality challenge

Yvon Savaria, Claude Thibeault, Andre Ivanov, 1996 .

FPGA implementation of Token-based Self-timed processors: A case study

Yvon Savaria, Claude Thibeault, Mickael Fiorentino, 2017, 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS).

A 237 Gbps Unrolled Hardware Polar Decoder pdf

Warren J. Gross, Claude Thibeault, Gabi Sarkis, 2014, ArXiv.

Efficient multi-abstraction level functional verification methodology for DSP applications

Zeljko Zilic, Claude Thibeault, Jean-François Boland, 2005 .

Yield modeling of a WSI telecom router architecture

Yvon Savaria, Chunyan Wang, Claude Thibeault, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Unrolled Hardware Architectures for Polar Decoders

Warren J. Gross, Claude Thibeault, Pascal Giard, 2017 .

A neuromimetic ultra low-power ADC for bio-sensing applications

Mohamad Sawan, Claude Thibeault, My El Mustapha Ait Yakoub, 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.

Unrolled Polar Decoders, Part I: Hardware Architectures pdf

Warren J. Gross, Claude Thibeault, Gabi Sarkis, 2015, ArXiv.

3DSDM: A 3 data-source diagnostic method

Claude Thibeault, Yassine Hariri, C. Thibeault, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Fast Low-Complexity Decoders for Low-Rate Polar Codes

Alexios Balatsoukas-Stimming, Warren J. Gross, Claude Thibeault, 2016, J. Signal Process. Syst..

A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits

Yvon Savaria, Claude Thibeault, Jean-Louis Houle, 1994, IEEE Trans. Computers.

Comparing results from defect-tolerant yield models

Claude Thibeault, Yvon Savaria, 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Fault tolerant flight control system using emmae method and reconfiguration with sliding mode technique

Maarouf Saad, Claude Thibeault, Jean-François Boland, 2012, 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

Towards a realistic SEU effects emulation on SRAM based FPGAs

Claude Thibeault, Raoul Velazco, Yves Blaquiere, 2014 .

On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults

Claude Thibeault, C. Thibeault, 2000, IEEE Trans. Computers.

FPGA Implementation of a new decoder algorithm for convolutional codes

Claude Thibeault, Francois Gagnon, Naim Batani, 1995 .

Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results

Claude Thibeault, C. Thibeault, 2000, J. Electron. Test..

A practical design method for prototyping self-timed processors using FPGAs

Yvon Savaria, Claude Thibeault, Mickael Fiorentino, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage

Yvon Savaria, Claude Thibeault, Omar Al-Terkawi Hasib, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes

Alexander Vardy, Ido Tal, Warren J. Gross, 2016, IEEE Transactions on Communications.

${\rm C}\Delta{\rm IDDQ}$: Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation

Claude Thibeault, Yassine Hariri, C. Thibeault, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Using Fourier analyses to enhance IC testability

Claude Thibeault, 1994, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

From synchronous to GALS: A new architecture for FPGAs

Claude Thibeault, Jean Belzile, René Gagné, 2009, Microelectron. J..

On the Comparison of IDDQ and IDDQ Testing

Claude Thibeault, 1999, VTS.

Detection and location of faults and defects using digital signal processing

Claude Thibeault, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Tools for the characterization of bipolar CML testability

Yvon Savaria, Claude Thibeault, Pieter M. Trouborst, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization

Yvon Savaria, Claude Thibeault, Guchuan Zhu, 2012 .

Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits

Yvon Savaria, Claude Thibeault, Omar Al-Terkawi Hasib, 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results

Claude Thibeault, Luc Boisvert, C. Thibeault, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Design of a tolerant flight control system in response to multiple actuator control signal faults induced by cosmic rays

Maarouf Saad, Claude Thibeault, J.-F. Boland, 2016, IEEE Transactions on Aerospace and Electronic Systems.

A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs

Warren J. Gross, Claude Thibeault, Gabi Sarkis, 2015, 2015 IEEE Workshop on Signal Processing Systems (SiPS).

Multi-Mode reconfigurable Software Defined Radio architecture for avionic radios

Claude Thibeault, René Landry, Alireza Avakh Kisomi, 2017, 2017 Integrated Communications, Navigation and Surveillance Conference (ICNS).

Efficient diagnosis of single/double bridging faults with Delta Iddq probabilistic signatures and Viterbi algorithm

Claude Thibeault, C. Thibeault, 2000, Proceedings 18th IEEE VLSI Test Symposium.

An LPI design for secure OFDM systems

François Gagnon, Georges Kaddoum, Claude Thibeault, 2012, MILCOM 2012 - 2012 IEEE Military Communications Conference.

DME/DME navigation using a single low-cost SDR and sequential operation

Wessam Ajib, Claude Thibeault, Omar A. Yeste-Ojeda, 2014, 2014 IEEE/AIAA 33rd Digital Avionics Systems Conference (DASC).

A methodology for system-level fault injection based on gate-level faulty behavior

Yvon Savaria, Claude Thibeault, J.-F. Boland, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

On Extra Delays Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiation

Yvon Savaria, Claude Thibeault, Yves Audet, 2014, IEEE Transactions on Nuclear Science.

Low complexity low power non-recursive digital filters with unconstrained topology

François Gagnon, Michel Gendreau, Claude Thibeault, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

Hardware decoders for polar codes: An overview

Chi-Ying Tsui, Alexios Balatsoukas-Stimming, Andreas Peter Burg, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Self-timed circuits FPGA implementation flow

Yvon Savaria, Claude Thibeault, Omar Al-Terkawi Hasib, 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

Using sinusoidal stimuli and Fourier analyses for memory IC testing

Claude Thibeault, 1994, Proceedings of IEEE International Workshop on Memory Technology, Design, and Test.

Low-Latency Software Polar Decoders

Warren J. Gross, Claude Thibeault, Camille Leroux, 2015, J. Signal Process. Syst..

A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design

Yvon Savaria, Claude Thibeault, Syed Rafay Hasan, 2013, J. Electron. Test..

Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits

Yvon Savaria, Claude Thibeault, Jean-Louis Houle, 1995, IEEE Trans. Computers.

Experimental results from I/sub DDF/ testing

Claude Thibeault, A. Payeur, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

FFT-based test of a yield monitor circuit

Claude Thibeault, A. Payeur, 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

Replacing IDDQ Testing: With Variance Reduction

Claude Thibeault, 2003, J. Electron. Test..

Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications

Yvon Savaria, Claude Thibeault, Otmane Aït Mohamed, 2014, 2014 Twelfth ACM/IEEE Conference on Formal Methods and Models for Codesign (MEMOCODE).

Speeding-up I/sub DDQ/ measurements

Claude Thibeault, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

On the use of wavelet analysis for IC testing

Claude Thibeault, Christian Gargour, Aminata Dia, 1999 .

A multifunction signal processing card with FPD's

Claude Thibeault, Naim Batani, Fred Awad, 1995 .

WeSPer: A flexible small delay defect quality metric

Yvon Savaria, Claude Thibeault, Omar Al-Terkawi Hasib, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline

François Gagnon, Ghyslain Gagnon, Claude Thibeault, 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.

Improving Delta-I/sub DDQ/-based test methods

Claude Thibeault, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation

Yves Blaquière, Claude Thibeault, Yves Audet, 2014, IEEE Transactions on Nuclear Science.

Multi-Mode Unrolled Architectures for Polar Decoders

Warren J. Gross, Claude Thibeault, Gabi Sarkis, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design experience from system level to FPGAs

Claude Thibeault, Francois Gagnon, 1995 .

A System Architecture for Smart Sensors Integration in Avionics Applications

Yvon Savaria, Claude Thibeault, Guchuan Zhu, 2012 .

SLIDING MODE RECONFIGURABLE CONTROL FOR COSMIC RAYS FAULTS IN FLIGHT SYSTEMS

Maarouf Saad, Claude Thibeault, Jean-François Boland, 2014 .

Building Heterogeneous Functional Prototypes Using Articulated Interfaces Regroupement Straten Micro´ electronique du Qu´ (ReSMiQ)

Zeljko Zilic, Claude Thibeault, Y. Savaria, 2006 .

Some results on yield and local design rule relaxation

Yvon Savaria, Claude Thibeault, J. Crépeau, 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Introducing KeyRing self-timed microarchitecture and timing-driven design flow

Yvon Savaria, Claude Thibeault, Mickaël Fiorentino, 2021, IET Comput. Digit. Tech..

Design of low complexity multiplierless digital filters with optimized free structure using a population-based metaheuristic

Michel Gendreau, Claude Thibeault, Francois Gagnon, 2011, ISSCS 2011 - International Symposium on Signals, Circuits and Systems.

Fault tolerant smart transducer interfaces for safety-critical avionics applications

Yvon Savaria, Claude Thibeault, Guchuan Zhu, 2013, 2013 IEEE/AIAA 32nd Digital Avionics Systems Conference (DASC).

Towards Analysis of the Radiation Sensitivity of Digital Designs at High Level of Abstraction

Christophe Jégo, Claude Thibeault, Claude Thibeault, 2015 .