Nam Ho

发表

Evolution of application-specific cache mappings

Marco Platzner, Nam Ho, Paul Kaufmann, 2020, Int. J. Hybrid Intell. Syst..

MemMON: run-time off-chip detection for memory access violation in embedded systems

Anh-Vu Dinh-Duc, Nam Ho, 2010, SoICT '10.

Evaluation of Parameters Affecting the Performance of Routing Protocols in Mobile Ad Hoc Networks (MANETs) with a Focus on Energy Efficiency

Nam Ho, Nahid Ebrahimi Majd, Thu Nguyen, 2019, Lecture Notes in Networks and Systems.

FPGA-based reconfigurable cache mapping schemes: design and optimization

Nam Ho, 2018 .

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions

Nam Ho, Roberto Giorgi, Alberto Scionti, 2015, 2015 Euromicro Conference on Digital System Design.

A hardware/software approach to detect memory corruptions in embedded systems

Anh-Vu Dinh-Duc, Nam Ho, 2010, The 2010 International Conference on Advanced Technologies for Communications.

Enhancing an x86_64 multi-core architecture with data-flow execution support

Nam Ho, Roberto Giorgi, Alberto Scionti, 2015, Conf. Computing Frontiers.

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings

Marco Platzner, Paul Kaufmann, Nam Ho, 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

A run-time detector for violated memory access in embedded systems

Anh-Vu Dinh-Duc, Nam Ho, 2010, Proceedings of 2010 IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications.

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms

Marco Platzner, Paul Kaufmann, Nam Ho, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches

Marco Platzner, Paul Kaufmann, Nam Ho, 2017, 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure

Marco Platzner, Paul Kaufmann, Nam Ho, 2014, 2014 IEEE International Conference on Evolvable Systems.

Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor

Marco Platzner, Paul Kaufmann, Nam Ho, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor

Marco Platzner, Nam Ho, Paul Kaufmann, 2019, SoCPaR.

Secure MQTT Protocol based on Attribute-Based Encryption Scheme

Choong Seon Hong, Nam Ho, 2018 .

Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor

Marco Platzner, Paul Kaufmann, Nam Ho, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Multilevel simulation-based co-design of next generation HPC microprocessors

Polydoros Petrakis, Lilia Zaourar, Nam Ho, 2021, 2021 International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS).

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors

Nam Ho, Romain Lemaire, Pedro Marcuello, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).