Yoshinobu Higami

发表

Enhancement of Clock Delay Faults Testing

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2011, 2011 Sixteenth IEEE European Test Symposium.

Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2012, J. Networks.

Diagnosis for Multiple Stuck-at Faults by Ambiguous Test Set

Yuzo Takamatsu, Yoshinobu Higami, Yukihiro Yamamoto, 2004 .

Regeneration of Test Patterns for BIST by Using Artificial Neural Networks

Yoshinobu Higami, Tsutomu Inamoto, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Output voltage estimation of a floating interconnect line caused by a hard open in 90nm ICs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2010, 2010 10th International Symposium on Communications and Information Technologies.

Diagnosis for Bridging Faults on Clock Lines

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2004, IEICE Trans. Inf. Syst..

A partial scan algorithm based on reduced scan shift

Kozo Kinoshita, Yoshinobu Higami, S. Kajihara, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Giving formal roles to elevators for breaking symmetry in static elevator operation problems

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2014, Int. J. Netw. Comput..

Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2008 .

Sushi: A Lightweight Distributed Image Storage System for Mobile and Web Services

Yoshinobu Higami, Shin-ya Kobayashi, Kamoliddin Mavlonov, 2014, ACS.

On the fault diagnosis in the presence of unknown fault models using pass/fail information

Yuzo Takamatsu, Yoshinobu Higami, Kazuo Yamazaki, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Test Pattern Selection for Defect-Aware Test

Hiroshi Furutani, Hiroshi Takahashi, Yoshinobu Higami, 2011, 2011 Asian Test Symposium.

Feasibility of Machine Learning Algorithm for Test Partitioning

Yoshinobu Higami, Hiroshi Takahashi, Senling Wang, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Fault models and test generation for IDDQ testing: embedded tutorial

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, ASP-DAC.

Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262

Yoichi Maeda, Hiroshi Takahashi, Yoshinobu Higami, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Test cost reduction for logic circuits: Reduction of test data volume and test application time

Yuzo Takamatsu, Yoshinobu Higami, Seiji Kajihara, 2005 .

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool

Hiroshi Takahashi, Yoshinobu Higami, Yoshihiro Shimizu, 2012, IEICE Trans. Inf. Syst..

New Class of Tests for Open Faults with Considering Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2009, 2009 Asian Test Symposium.

Design and Implementation of Data Synchronization and Offline Capabilities in Native Mobile Apps

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2016, ACIIDS.

Reduction of Fault Dictionary Size by Optimizing the Order of Test Patterns Application

Kewal K. Saluja, Yoshinobu Higami, Hiroshi Takahashi, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD)

Masayuki Sato, Hiroshi Takahashi, Yoshinobu Higami, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Energy Aware MPR Selection Mechanism in OLSR-based Mobile Ad Hoc Networks

Yoshinobu Higami, Shin-ya Kobayashi, Wardi, 2010 .

Development of Concealing the Purpose of Processing for Programs in a Distributed Computing Environment

Yoshinobu Higami, Shin-ya Kobayashi, Koichi Kashiwagi, 2007, Advances in Information Processing and Protection.

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2010, J. Commun..

Harnessing Fuzziness of the Pragmatic Rule-Design Without IF-THEN Rules

Yoshinobu Higami, Tsutomu Inamoto, 2017, FSDM.

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2017, IEICE Trans. Inf. Syst..

Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications

Yoshinobu Higami, Shin-ya Kobayashi, Dai Okano, 2017, ACIIDS.

Failure analysis of open faults by using detecting/un-detecting information on tests

Yuichi Sato, Hiroshi Takahashi, Yuzo Takamatsu, 2004, 13th Asian Test Symposium.

Diagnosis of Delay Faults in the Presence of Clock Delays Considering Hazards

Kewal K. Saluja, Hiroshi Takahashi, Yoshinobu Higami, 2015 .

Static test compaction for IDDQ testing of sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1998, Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232).

A Study to Reduce the Life Cycle Cost of the Railway Signaling System that Considered the Economic Loss Cost that the Equipment Fault Gave to Passengers

Hiroshi Shida, Hirofumi Oogushi, Hiroshi Takahashi, 2016 .

Application of Convolutional Neural Networks to Regenerate Deterministic Test Patterns for BIST

Yoshinobu Higami, Tsutomu Inamoto, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Simulated Annealing based Pattern Selection Method to Handle Power Supply Noise for Resistive Open Fault Diagnosis

Hiroshi Takahashi, Yoshinobu Higami, Senling Wang, 2015 .

Partial scan design and test sequence generation based on reduced scan shift method

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1995, J. Electron. Test..

A method to find don't care values in test sequences for sequential circuits

Irith Pomeranz, Yuzo Takamatsu, Yoshinobu Higami, 2003, Proceedings 21st International Conference on Computer Design.

Techniques for finding Xs in test sequences for sequential circuits and applications to test length/power reduction

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2004, 13th Asian Test Symposium.

A method to reduce power dissipation during test for sequential circuits

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Timing-Aware Diagnosis for Small Delay Defects

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

The analysis of Automated HTML5 Offline Services (AHOS)

Yoshinobu Higami, Shinya Kobayashi, Zulkifli Tahir, 2015, 2015 International Conference on Intelligent Informatics and Biomedical Sciences (ICIIBMS).

Evaluation of Influence Exerted by a Malicious Group's Various Aims in the External Grid

Yoshinobu Higami, Tsutomu Inamoto, Shinya Kobayashi, 2016, ACS.

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000 .

Replica selection scheme with backward reservation in optical grid networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2009 .

Aging Monitoring for Memory-based ReconFigurable Logic Device (MRLD)

Yoshinobu Higami, Hiroshi Takahashi, Senling Wang, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2008, IEICE Trans. Inf. Syst..

Foreword: Special section on VLSI design and CAD algorithms

Yuichiro Shibata, Makoto Ikeda, Hiroyuki Tomiyama, 2014 .

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2017, 2017 17th International Symposium on Communications and Information Technologies (ISCIT).

Diagnosis of Delay Faults Considering Hazards

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

A Consideration of Processor Utilization on Multi-Processor System

Yoshinobu Higami, Shin-ya Kobayashi, Koichi Kashiwagi, 2007, Advances in Information Processing and Protection.

Modifying test vectors for reducing power dissipation in CMOS circuits

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

L-024 Evaluation of advance processing in terms of processing time on Secure Processing

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2015 .

The User Interface of the Autonomous Load Distribution Algorithm For General Users

Yoshinobu Higami, Shin-ya Kobayashi, Shunsuke Kuhara, 2004 .

Test generation for double stuck-at faults

Yuzo Takamatsu, Yoshinobu Higami, Naoko Takahashi, 2001, Proceedings 10th Asian Test Symposium.

Test sequence compaction by reduced scan shift and retiming

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1995, Proceedings of the Fourth Asian Test Symposium.

Enhancing BIST based single/multiple stuck-at fault diagnosis by ambiguous test set

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2004, 13th Asian Test Symposium.

Problems and Solutions on IDDQ Testing

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2003 .

Improvement of the processors operating ratio in task scheduling using the deadline method

Yoshinobu Higami, Shin-ya Kobayashi, Koichi Kashiwagi, 2005, Enhanced Methods in Computer Security, Biometric and Artificial Intelligence Systems.

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2013, IEICE Trans. Inf. Syst..

Improvement and evaluation of autonomous load distribution method

Yoshinobu Higami, Shin-ya Kobayashi, Yugo Ito, 2003 .

Road-Map to Bridge Theoretical and Practical Approaches for Elevator Operations

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2016, 2016 5th IIAI International Congress on Advanced Applied Informatics (IIAI-AAI).

Diagnostic test generation for transition faults using a stuck-at ATPG tool

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2009, 2009 International Test Conference.

Diagnosis for Open Faults Based on Detecting/Un-detecting Information on Ambiguous Test Set

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2005 .

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Dynamic routing and wavelength assignment in multifiber WDM networks with sparse wavelength conversion

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2012, 2012 International Conference on ICT Convergence (ICTC).

Observation time reduction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Test Sequence Generation for Sequential Circuits with Distinguishing Sequences (Special Section on VLSI Design and CAD Algorithms)

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1993 .

Preliminary Analysis of Interconnect Full Open Faults using TEG chips

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009 .

Accurate resistance measuring method for high density post-bond TSVs in 3D-SIC with Electrical Probes

Yoshinobu Higami, Shuichi Kameyama, Hiroshi Takahashi, 2014, 2014 International Conference on Electronics Packaging (ICEP).

Injecting speculation on ideal trajectories into a trip-based integer programming model for elevator operations

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2013, 2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE).

Program Committee

Michael S. Hsiao, Irith Pomeranz, Nur A. Touba, 2006, WOWMOM.

On Detecting Transition Faults in the Presence of Clock Delay Faults

Kewal K. Saluja, Yoshinobu Higami, Shin-ya Kobayashi, 2011, 2011 Asian Test Symposium.

Dynamic routing and wavelength assignment scheme using signaling of backward reservation in multifiber WDM networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2011, ICTC 2011.

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, Systems and Computers in Japan.

Wavelength selection based on wavelength availability in multi-fiber WDM networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2011, 2011 International Conference on Multimedia Technology.

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation

Masaki Hashizume, Hiroshi Takahashi, Kewal K. Saluja, 2013, 2013 22nd Asian Test Symposium.

Trends in 3D Integrated Circuit (3D-IC) Testing Technology

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015 .

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Evaluation of educational applications in terms of communication delay between tablets with Bluetooth or Wi-Fi Direct

Yoshinobu Higami, Dai Okano, Shinya Kobayashi, 2018, Vietnam Journal of Computer Science.

Efficient techniques for reducing IDDQ observation time for sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Effective Post-BIST Fault Diagnosis for Multiple Faults

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

A method for diagnosing resistive open faults with considering adjacent lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2010, 2010 10th International Symposium on Communications and Information Technologies.

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2008, IEICE Trans. Inf. Syst..

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Reduced scan shift: a new testing method for sequential circuits

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1994, Proceedings., International Test Conference.

Test cost reduction for logic circuits: Reduction of test data volume and test application time

Yuzo Takamatsu, Yoshinobu Higami, Seiji Kajihara, 2005, Systems and Computers in Japan.

Fault simulation techniques to reduce IDDQ measurement vectors for sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays

Kewal K. Saluja, Yoshinobu Higami, Shin-ya Kobayashi, 2016, IPSJ Trans. Syst. LSI Des. Methodol..

Test sequence compaction for sequential circuits with reset states

Kozo Kinoshita, Yuzo Takamatsu, Yoshinobu Higami, 2000, Proceedings of the Ninth Asian Test Symposium.

Reliability of Node Information on Autonomous Load Distribution Method

Yoshinobu Higami, Shin-ya Kobayashi, Koichi Kashiwagi, 2007, Advances in Information Processing and Protection.

Dummy code insertion and its efforts on concealment for secure processing

Yoshinobu Higami, Shin-ya Kobayashi, Hiroshi Kai, 2012 .

D-040 Automatic determination of compatibility of method invocations in object-oriented database systems

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2009 .

Test Generation for Sequential Circuits under IDDQ Testing

Taro Maeda, Yoshinobu Higami, K. Kinosita, 1998 .

Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

A Novel Approach for Improving the Quality of Open Fault Diagnosis

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009, 2009 22nd International Conference on VLSI Design.

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, J. Electron. Test..

An effective dynamic parallel downloading scheme with network coding in λ-grid networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2009, 2009 First Asian Himalayas International Conference on Internet.

Partially parallel scan chain for test length reduction by using retiming technique

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

Post-BIST Fault Diagnosis for Multiple Faults

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2008, IEICE Trans. Inf. Syst..

Simulation-based diagnosis for crosstalk faults in sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2001, Proceedings 10th Asian Test Symposium.

RE-OLSR: Residual Energy-Based OLSR Protocol in Mobile Ad Hoc Networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2011 .

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST

Yoichi Maeda, Hiroshi Takahashi, Yoshinobu Higami, 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

RE-OLSR: Residual Energy-Based OLSR Protocol

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2011 .

Dynamic Parallel Downloading with Network Coding in $\lambda$-Grid Networks

Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi, 2010, J. Commun..

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2009, IPSJ Trans. Syst. LSI Des. Methodol..

Residual energy-based OLSR in mobile ad hoc networks

Yoshinobu Higami, Shin-ya Kobayashi, Kouji Hirata Wardi, 2011, 2011 International Conference on Multimedia Technology.

Optimistic Processing Protocol for Multiplexing in External PC Grids

Yoshinobu Higami, S. Kobayashi, A. Funo, 2010 .

On Finding Don't Cares in Test Sequences for Sequential Circuits

Irith Pomeranz, Yuzo Takamatsu, Yoshinobu Higami, 2006, IEICE Trans. Inf. Syst..

Decreasing computational times for solving static elevator operation problems by assuming maximum waiting times

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2014, 2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE).

Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing

Takahashi Hiroshi, Yoshinobu Higami, Matsushima Jun, 2020 .

Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2013, 2013 First International Symposium on Computing and Networking.

Fault simulation and test generation for clock delay faults

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

M-027 Development of the Smartphone Application to Choose and Display News for Individuals based on an Operation History

Yoshinobu Higami, Shin-ya Kobayashi, Satoshi Ono, 2015 .

Compaction of Test Vectors for IDDQ Testing of Sequential Circuits

Kewal K. Saluja, Yuzo Takamatsu, Yoshinobu Higami, 2000 .

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009, 2009 22nd International Conference on VLSI Design.

Compact Dictionaries for Reducing Compute Time in Adaptive Diagnosis

Kewal K. Saluja, Yoshinobu Higami, Hiroshi Takahashi, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Design of partially parallel scan chain

Kozo Kinoshita, Yoshinobu Higami, 1997, Proceedings European Design and Test Conference. ED & TC 97.

A call-based integer programming model for static elevator operation problems

Yoshinobu Higami, Shin-ya Kobayashi, Tsutomu Inamoto, 2014, 2014 Joint 7th International Conference on Soft Computing and Intelligent Systems (SCIS) and 15th International Symposium on Advanced Intelligent Systems (ISIS).

Improving the Diagnostic Quality of Open Faults

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2008 .

A Reduced Scan Shift Method for Sequential Circuit Testing (Special Section on VLSI Design and CAD Algorithms)

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1994 .